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Data Sheet

AD5689/AD5687

Rev. B | Page 17 of 24

THEORY OF OPERATION

19B

DIGITAL-TO-ANALOG CONVERTERS (DACS)

The AD5689/AD5687 are dual 16-/12-bit, serial input, voltage

output DACs. The parts operate from supply voltages of 2.7 V to

5.5 V. Data is written to the AD5689/AD5687 in a 24-bit word

format via a 3-wire serial interface. The devices incorporate a

power-on reset circuit to ensure that the DAC output powers up

to a known output state. The AD5689/AD5687 also have a

software power-down mode that reduces the typical current

consumption to 4 µA.

20B

TRANSFER FUNCTION

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by









REF

OUT

Gain

where:

Gain is the output amplifier gain and is set to 1 by default. It can

be set to ×1 or ×2 using the gain select pin. When the GAIN pin

is tied to GND, both DACs output a span from 0 V to VREF. If

the GAIN pin is tied to VLOGIC, both DACs output a span of 0 V

to 2 × VREF.

D is the decimal equivalent of the binary code that is loaded to

the DAC register as follows: 0 to 4,095 for the 12-bit device and

0 to 65,535 for the 16-bit device.

N is the DAC resolution.

21B

DAC ARCHITECTURE

The DAC architecture consists of a string DAC followed by an

output amplifier. Figure 36 shows a block diagram of the DAC

architecture.

INPUT

DAC

RESISTOR

STRING

REF (+)

VREF

GND

REF (–)

VOUTX

GAIN

(GAIN = 1 OR 2)

Figure 36. Single DAC Channel Architecture Block Diagram

The resistor string structure is shown in Figure 37. It is a string

of resistors, each of Value R. The code loaded to the DAC register

determines the node on the string where the voltage is to be

tapped off and fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the

string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

TO OUTPUT

AMPLIFIER

VREF

Figure 37. Resistor String Structure

39B

Output Amplifiers

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to VDD. The actual

range depends on the value of VREF, the GAIN pin, the offset

error, and the gain error. The GAIN pin selects the gain of the

output, as follows:

•

If the GAIN pin is tied to GND, both DAC outputs have

a gain of 1, and the output range is 0 V to VREF.

•

If the GAIN pin is tied to VLOGIC, both DAC outputs have

a gain of 2, and the output range is 0 V to 2 × VREF.

These amplifiers are capable of driving a load of 1 kΩ in parallel

with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale

settling time of 5 µs.

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