IXDR502D1B datasheet(4/11 Pages) IXYS

4 / 11 page

IXDR502 / IXDS502

Unless otherwise noted, 4.5V

≤ V

CC ≤ 22V , Tj < 150

All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions.

Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

VIH

High input voltage

4.5V

≤ V

CC ≤ 15V

3.5

VIL

Low input voltage

4.5V

≤ V

CC ≤ 15V

0.8

VIN

Input voltage range

-5

VCC + 0.3

IIN

Input current

≤ V

IN ≤ VCC

-20

µA

VOH

High output voltage

VCC - 0.05

VOL

Low output voltage

0.05

ROH

Output resistance

@ Output high

VCC = 15V

Ω

ROL

Output resistance

@ Output Low

VCC = 15V

Ω

IDC

Continuous output

current

0.3

Rise time

CL=1000pF Vcc=15V

Fall time

CL=1000pF Vcc=15V

tONDLY

On-time propagation

delay

CL=1000pF Vcc=15V

tOFFDLY

Off-time propagation

delay

CL=1000pF Vcc=15V

VCC

Power supply voltage

4.5

ICC

Power supply current

VIN = 3.5V

VIN = 0V

VIN = + VCC, (4.5V≤ VCC ≤ 18V)

µA

Notes:

1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent

damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

2. The device is not intended to be operated outside of the Operating Ratings.

3. Electrical Characteristics provided are associated with the stated Test Conditions.

4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily

to highlight any specific performance limits within which the device is guaranteed to function.

* The following notes are meant to define the conditions for the θ

J-A, θJ-C and θJ-S values:

1) The

J-A (typ) is defined as junction to ambient.

The

J-A

of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated

by the resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with

vertical boards and the values would be lower with forced convection. For the 6-Lead DFN package, the

J-A value supposes the DFN

package is soldered on a PCB. The

J-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad

provides a low thermal resistance to the die, it is easy to reduce the

J-A by adding connected copper pads or traces on the PCB.

These can reduce the

J-A (typ) to 125 °C/W easily, and potentially even lower.

The

J-A for DFN on PCB without heatsink or thermal

management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what they are likely

to get if no thermal management is done.

J-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package.

The

J-C values are generally

not published for the PDIP and SOIC packages. The

J-C for the DFN packages are important to show the low thermal resistance from

junction to the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.

3) The

J-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a

heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily

available IMS in the U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was

assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential

low thermal resistance for the DFN package.

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