LTC2249 datasheet(13/20 Pages) LINER

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LTC2249

2249f

APPLICATIO S I FOR ATIO

The noise performance of the LTC2249 can depend on the

clock signal quality as much as on the analog input. Any

noise present on the clock signal will result in additional

aperture jitter that will be RMS summed with the inherent

ADC aperture jitter.

In applications where jitter is critical, such as when digitiz-

ing high input frequencies, use as large an amplitude as

possible. Also, if the ADC is clocked with a sinusoidal

signal, filter the CLK signal to reduce wideband noise and

distortion products generated by the source.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2249 is 80Msps.

For the ADC to operate properly, the CLK signal should

have a 50% (±5%) duty cycle. Each half cycle must have

at least 5.9ns for the ADC internal circuitry to have enough

settling time for proper operation.

An optional clock duty cycle stabilizer circuit can be used

if the input clock has a non 50% duty cycle. This circuit

uses the rising edge of the CLK pin to sample the analog

input. The falling edge of CLK is ignored and the internal

falling edge is generated by a phase-locked loop. The input

clock duty cycle can vary from 40% to 60% and the clock

duty cycle stabilizer will maintain a constant 50% internal

duty cycle. If the clock is turned off for a long period of

time, the duty cycle stabilizer circuit will require a hundred

clock cycles for the PLL to lock onto the input clock. To use

the clock duty cycle stabilizer, the MODE pin should be

connected to 1/3VDD or 2/3VDD using external resistors.

Input Range

The input range can be set based on the application. The

2V input range will provide the best signal-to-noise perfor-

mance while maintaining excellent SFDR. The 1V input

range will have better SFDR performance, but the SNR will

degrade by 5.7dB. See the Typical Performance Charac-

teristics section.

Driving the Clock Input

The CLK input can be driven directly with a CMOS or TTL

level signal. A sinusoidal clock can also be used along with

a low-jitter squaring circuit before the CLK pin (see

Figure 11).

VCM

REFH

SENSE

TIE TO VDD FOR 2V RANGE;

TIE TO VCM FOR 1V RANGE;

RANGE = 2 • VSENSE FOR

0.5V < VSENSE < 1V

1.5V

REFL

2.2µF

INTERNAL ADC

HIGH REFERENCE

BUFFER

0.1µF

2249 F09

LTC2249

4Ω

DIFF AMP

1µF

INTERNAL ADC

LOW REFERENCE

1.5V BANDGAP

REFERENCE

0.5V

RANGE

DETECT

AND

CONTROL

Figure 9. Equivalent Reference Circuit

VCM

SENSE

1.5V

0.75V

2.2µF

12k

1µF

12k

2249 F10

LTC2249

Figure 10. 1.5V Range ADC

CLK

50Ω

0.1µF

4.7µF

FERRITE

BEAD

CLEAN

SUPPLY

SINUSOIDAL

CLOCK

INPUT

2249 F11

NC7SVU04

LTC2249

Figure 11. Sinusoidal Single-Ended CLK Drive

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