SC16C652B datasheet(13/44 Pages) PHILIPS

13 / 44 page

Philips Semiconductors

SC16C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

Product data

Rev. 03 — 10 December 2004

13 of 44

9397 750 14452

6.9 DMA operation

The SC16C652B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. The user can optionally operate the transmit and receive FIFOs in

the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY

output pins. Tables 7 and 8 show this.

6.10 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode,

the normal modem interface pins are disconnected and reconﬁgured for loop-back

internally (see Figure 5). MCR[0:3] register bits are used for controlling loop-back

diagnostic testing. In the loop-back mode, the transmitter output (TX) and the receiver

input (RX) are disconnected from their associated interface pins, and instead are

connected together internally. The CTS, DSR, CD, and RI are disconnected from

Table 6:

Baud rate generator programming table using a 1.8432 MHz clock

Output

baud rate

Output

× clock divisor

(decimal)

Output

× clock divisor

(HEX)

DLM

program value

(HEX)

DLL

program value

(HEX)

2304

900

1536

600

110

1047

417

150

768

300

384

180

600

192

1200

2400

3600

4800

7200

9600

19.2 k

38.4 k

57.6 k

115.2 k

Table 7:

Effect of DMA mode on state of RXRDY pin

Non-DMA mode

DMA mode

1 = FIFO empty

0-to-1 transition when FIFO empties

0 = at least 1 byte in FIFO

1-to-0 transition when FIFO reaches trigger level,

or time-out occurs

Table 8:

Effect of DMA mode on state of TXRDY pin

Non-DMA mode

DMA mode

1 = at least 1 byte in FIFO

0-to-1 transition when FIFO becomes full

0 = FIFO empty

1-to-0 transition when FIFO goes below trigger level

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