RSC4128 datasheet(13/49 Pages) ETC

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Data Sheet

RSC-4128

P/N 80-0206-J

to be the same or different from the processor clock used when the power-down flag was set. (see “Clock” section

for complete explanation)

To minimize power consumption, most operational blocks on the chip also have individual power controls that may

be selectively enabled or disabled by the programmer.

Wakeup from powerdown

Note that a Wakeup event does not cause a reset. The processor, which was "frozen" when register E8.Bit7 was

set, will be restarted without loss of context. A reset of the chip will also cancel a power down mode, but with a

corresponding loss of processor context.

Wakeup events terminate a power-down state. In Sleep mode, only an I/O Wakeup event can initiate a wake-up. In

Idle mode, an Audio Wakeup, I/O Wakeup or Timer2 interrupt request caused by overflow can generate a wakeup.

An I/O Wakeup is enabled by setting the bit(s) high in registers E9 or EA corresponding to the desired I/O pin(s) to

be used for wakeup. E9 controls P0 wakeup enable and EA controls P1 wakeup enable. The polarity of the

wakeup event is controlled by putting the appropriate port pin in input mode and writing the appropriate bit in the

output register for that pin to the desired polarity. (see “General Purpose I/O” section for complete explanation)

When the value on the wakeup pin equals the value in the output register a wakeup will occur.

A T2 Wakeup is enabled by setting register E8.Bit6 high. Then an overflow of timer T2 will generate an interrupt

request, which in turn will trigger a wakeup event. Note that the Timer2 “irq” bit (register FE.Bit1) must be cleared

prior to powering down to allow the wakeup interrupt request to occur. (the “Timers/Counters” section describes

how timer T2 is configured)

An Audio Wakeup is generated by special circuitry that can detect several classes of sounds, even while in power-

down mode. When the class of sound selected by the programmer is detected by this circuitry a wakeup event will

occur. (see the “Audio Wakeup” section for more information)

General Purpose I/O

The RSC-4128 has 24 general-purpose I/O pins (P0.0-P0.7, P1.0-P1.7, P2.0-P2.7). Each pin can be programmed

as an input with weak pull-up (~200k

Ω equivalent device); input with strong pull-up (~10kΩ equivalent device); input

without pull-up, or as an output with sufficient drive to light an LED. (See “DC Characteristics” section for I/O

electrical characteristics.) This is accomplished by programming combinations of 48 bits of configuration registers

assigned to the I/O pins.

Two control registers, A and B, are used to control the nature of inputs and outputs for each port. Registers E6

(“p0CtlA”) and E7 (“p0CtlB”), E2 (“p1CtlA”) and E3 (“p1CtlB”), and DE (“p2CtlA”) and DF (“p2CtlB”), are the control

registers A and B for ports P0, P1 and P2, respectively. Each port pin’s I/O configuration may be controlled

independently by the state of it’s corresponding bits in these registers. Control registers A and B together

determine the function of the port pins as follows:

B bit

A bit

Port Pin Function

Input - Weak Pull-up

Input - Strong Pull-up

Input - No pull-up

Output

(For example, if register E7.Bit 4 is set high, and register E6.Bit 4 is low, then pin P0.4 is an input without a pull-up

device.)

After reset, pins P0.0-P0.7, P1.0-P1.7, and P2.5-P2.7 are set to be digital inputs with weak pull-ups, and pins P2.0-

P2.4 are configured as analog input pins with no pull-ups. Being reset as an input and lightly pulled to a known

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