AM6548 datasheet(252/299 Pages) TI1

252 / 299 page

252

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

•

Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)

•

Provides 1 memory write access unit (Write Unit 0):

–

Supports write bursts up to 32 bytes (limited by Tx Per-Channel FIFO depth)

–

Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses.

–

Supports up to 8 outstanding writes

•

Provides 1 memory read access unit

–

Supports 1 outstanding read per interface (VBUSP)

–

Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth)

–

Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses

•

Supports up to 3 simultaneous destination (Tx) channels

•

Supports up to 3 simultaneous source (Rx) channels

•

Supports static Transfer Requests (TRs) only

•

Supports MCAN special transfer mode

•

Provides per-channel buffering:

–

Provides 8x128-bit word deep data FIFO for each destination channel

–

Provides 8x128-bit word deep data FIFO for each source channel

–

Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals

–

Includes 1 output event transport lane

–

Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals

–

Includes 1 input event transport lane

6.10.1.1.3 PDMA0 Features

The MAIN domain PDMA0 supports the following features:

•

Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)

•

Provides 1 memory write access unit (Write Unit 0):

–

Supports write bursts up to 32 bytes (limited by Tx Per-Channel FIFO depth)

–

Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses

–

Supports up to 8 outstanding writes

•

Provides 1 memory read access unit (Read Unit 0):

–

Supports 1 outstanding read per interface (VBUSP)

–

Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth)

–

Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses

•

Supports up to 3 simultaneous destination (Tx) channels

•

Supports up to 3 simultaneous source (Rx) channels

•

Supports static Transfer Requests (TRs) only

•

Supports MCAN special transfer mode

•

Provides per-channel buffering:

–

Provides 8x128-bit word deep data FIFO for each destination channel

–

Provides 8x128-bit word deep data FIFO for each source channel

–

Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals

–

Includes 1 output event transport lane

–

Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals

–

Includes 1 input event transport lane

6.10.1.1.4 PDMA1 Features

The MAIN domain PDMA1 supports the following features:

•

Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)

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