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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM6548 датащи(PDF) 206 Page - Texas Instruments |
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AM6548 датащи(HTML) 206 Page - Texas Instruments |
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206 / 299 page  MMC1_CLK MMC1_CMD MMC1_DAT[3:0] HSSD1 HSSD2L HSSD2H HSSD3 HSSD4 HSSD7 HSSD8 MMC1_03 DSSD2 DSSD1 DSSD0 DSSD3 DSSD4 MMC1_CLK MMC1_CMD MMC1_DAT[3:0] MMC1_02 206 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Figure 5-77. MMC/SD in - Default Speed - Transmitter Mode 5.11.5.16.2.2 High speed, 4-bit data, SDR, half-cycle Table 5-73 and Table 5-74 present Timing requirements and Switching characteristics for MMC1 - High Speed in receiver and transmitter mode (see Figure 5-78 and Figure 5-79). Table 5-73. Timing Requirements for MMC1 - SD Card High Speed Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT HSSD3 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.96 ns HSSD4 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 2.67 ns HSSD7 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising clock edge Positive-edge Reference Clock 2.96 ns HSSD8 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising clock edge Positive-edge Reference Clock 2.67 ns Table 5-74. Switching Characteristics for MMC1 - SD Card High Speed Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT HSSD1 fop(clk) Operating frequency, MMC1_CLK Positive-edge Reference Clock 48 MHz HSSD2H tw(clkH) Pulse duration, MMC1_CLK high Positive-edge Reference Clock 9.6 ns HSSD2L tw(clkL) Pulse duration, MMC1_CLK low Negative-edge Reference Clock 9.6 ns HSSD5 td(clkL-cmdV) Delay time, MMC1_CLK falling clock edge to MMC1_CMD transition Negative-edge Reference Clock -7.5 3.5 ns HSSD6 td(clkL-dV) Delay time, MMC1_CLK falling clock edge to MMC1_DAT[3:0] transition Negative-edge Reference Clock -7.5 3.5 ns (1) P = output MMC1_CLK period in ns Figure 5-78. MMC/SD in - High Speed - Receiver Mode |
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