AM6548 datasheet(154/299 Pages) TI1

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VIN0_PCLK

(Negative-edge clocking)

VIN_DATA[15:0]

CAL_CCDC_TIMINGS_02

VIN0_PCLK

(Positive-edge clocking)

CAL_CCDC_TIMINGS_01

VIN0_PCLK

154

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

5.11.5 Peripherals

5.11.5.1 VIN

Table 5-28, Figure 5-26, and Figure 5-27 present timing requirements for LVDSRX interface.

Table 5-28. Timing Requirements for LVDSRX (1)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(PCLK)

Cycle time, VIN0_PCLK

Positive-edge

Reference Clock

5.76(1)

tw(PCLKH)

Pulse duration, VIN0_PCLK high

Positive-edge

Reference Clock

0.45 × P

(2)

tw(PCLKL)

Pulse duration, VIN0_PCLK low

Positive-edge

Reference Clock

0.45 × P

(2)

tsu(PCLK-CTL/DATA)

Input setup time, control (VIN0_HD, VIN0_VD) and

data (VIN0_DATA[15:0]) valid to VIN0_PCLK transition

Positive-edge

Reference Clock

2.38

th(CTL/DAT-PCLK)

Input hold time, control (VIN0_HD, VIN0_VD) valid to

VIN0_PCLK transition

Positive-edge

Reference Clock

-0.05

(1) For maximum frequency of 165 MHz

(2) P = VIN0_PCLK period

Figure 5-26. LVDSRX Input Clock Signal

Figure 5-27. LVDSRX Input Timings

5.11.5.2 CPSW2G

For more details about features and additional description information on the device Gigabit Ethernet

MAC, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed

Description.

5.11.5.2.1 CPSW2G MDIO Interface Timings

Table 5-29, Table 5-30, and Figure 5-28 present timing requirements for MDIO.

Table 5-29. Timing Requirements for MDIO Input

NO.

PARAMETER

MIN

MAX

UNIT

MDIO1

tsu(MDIO_MDC)

Setup time, MDIO_DATA valid before MDIO_CLK high

MDIO2

th(MDIO_MDC)

Hold time, MDIO_DATA valid after MDIO_CLK high

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