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ICS843256BGLF датащи(PDF) 8 Page - Integrated Device Technology |
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ICS843256BGLF датащи(HTML) 8 Page - Integrated Device Technology |
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8 / 16 page ![]() FemtoClock ® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 843256 DATA SHEET 8 REVISION B 12/18/14 APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843256 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC , V CCA , and V CCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10 μF and a .01μF bypass capacitor should be con- nected to each V CCA pin. FIGURE 1. POWER SUPPLY FILTERING 10 Ω V CCA 10 μF .01 μF 3.3V .01 μF V CC INPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. FIGURE 2. CRYSTAL INPUt INTERFACE C1 18p X1 18pF Parallel Crystal C2 22p XTAL_IN XTAL_OUT CRYSTAL INPUT INTERFACE The 843256 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were deter mined using an 18pF parallel resonant cr ystal and were chosen to minimize the ppm error. |
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