ADF4350

Data Sheet

Rev. B | Page 2 of 34

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications....................................................................................... 1

 

General Description ......................................................................... 1

 

Functional Block Diagram .............................................................. 1

 

Revision History ............................................................................... 2

 

Specifications..................................................................................... 3

 

Timing Characteristics ................................................................ 5

 

Absolute Maximum Ratings............................................................ 6

 

Transistor Count........................................................................... 6

 

ESD Caution.................................................................................. 6

 

Pin Configuration and Function Descriptions............................. 7

 

Typical Performance Characteristics ............................................. 9

 

Circuit Description......................................................................... 11

 

Reference Input Section............................................................. 11

 

RF N Divider ............................................................................... 11

 

INT, FRAC, MOD, and R Counter Relationship.................... 11

 

INT N MODE ............................................................................. 11

 

R Counter .................................................................................... 11

 

Phase Frequency Detector (PFD) and Charge Pump............ 11

 

MUXOUT and LOCK Detect................................................... 12

 

Input Shift Registers ................................................................... 12

 

Program Modes .......................................................................... 12

 

VCO.............................................................................................. 12

 

Output Stage................................................................................ 13

 

Register Maps .................................................................................. 14

 

Register 0 ..................................................................................... 18

 

Register 1 ..................................................................................... 18

 

Register 2 ..................................................................................... 18

 

Register 3 ..................................................................................... 20

 

Register 4 ..................................................................................... 20

 

Register 5 ..................................................................................... 20

 

Initialization Sequence .............................................................. 21

 

RF Synthesizer—A Worked Example ...................................... 21

 

Modulus....................................................................................... 21

 

Reference Doubler and Reference Divider ............................. 21

 

12-Bit Programmable Modulus................................................ 21

 

Cycle Slip Reduction for Faster Lock Times........................... 22

 

Spurious Optimization and Fast lock ...................................... 22

 

Fast-Lock Timer and Register Sequences ............................... 22

 

Fast Lock—An Example ............................................................ 22

 

Fast Lock—Loop Filter Topology............................................. 23

 

Spur Mechanisms ....................................................................... 23

 

Spur Consistency and Fractional Spur Optimization ........... 24

 

Phase Resync............................................................................... 24

 

Applications Information .............................................................. 25

 

Direct Conversion Modulator .................................................. 25

 

Interfacing ................................................................................... 26

 

PCB Design Guidelines for a Chip Scale Package ................. 26

 

Output Matching ........................................................................ 27

 

Outline Dimensions ....................................................................... 31

 

Ordering Guide .......................................................................... 31

 

REVISION HISTORY

5/16—Rev. A to Rev. B

Changes to Figure 3.......................................................................... 7

Changes to the ADuC7019 to ADuC7029 Family Interface

Section, Figure 35, and Figure 35 Caption .................................. 26

Updated Outline Dimensions ....................................................... 30

Changes to Ordering Guide .......................................................... 30

4/11—Rev. 0 to Rev. A

Changes to Typical rms Jitter in Features Section.........................1

Changes to Specifications.................................................................3

Changes Output Stage Section...................................................... 13

Changes to Figure 29...................................................................... 17

Changes to Fast Lock—An Example Section ............................. 22

Changes to Direct Conversion Modulator Section and

Figure 34 ......................................................................................... 25

Changes to ADuC70xx Interface Section and ADSP-BF527

Interface Section ............................................................................. 26

Changes to Output Matching Section and Table 7 .................... 27

Added Table 8 ................................................................................. 28

Changes to Ordering Guide .......................................................... 29

11/08—Revision 0: Initial Version