LTC6948 datasheet(21/38 Pages) AD

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LTC6948

6948fa

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operaTion

Figure 6. Serial Port Write Timing Diagram

Figure 8. Serial Port Write Sequence

Figure 7. Serial Port Read Timing Diagram

MASTER–CS

MASTER–SCLK

tCSS

tCS

tCH

DATA

6948 F06

tCKL

tCKH

tCSS

tCSH

MASTER–SDI

MASTER–CS

MASTER–SCLK

LTC6948–SDO

Hi-Z

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8TH CLOCK

DATA

tDO

the rising edge of SCLK, with all transfers MSB first. The

communicationburstisterminatedbytheserialbusmaster

returning CS high. See Figure 6 for details.

Data is read from the part during a communication burst

using SDO. Readback may be multidrop (more than one

LTC6948 connected in parallel on the serial bus), as SDO

is three-stated (Hi-Z) when CS = 1, or when data is not

being read from the part. If the LTC6948 is not used in

a multidrop configuration, or if the serial port master is

not capable of setting the SDO line level between read

sequences, it is recommended to attach a high value

resistor of greater than 200k between SDO and GND to

ensure the line returns to a known level during Hi-Z states.

See Figure 7 for details.

Single Byte Transfers

The serial port is arranged as a simple memory map, with

status and control available in 15 byte-wide registers. All

data bursts are comprised of at least two bytes. The seven

mostsignificantbitsofthefirstbytearetheregisteraddress,

with an LSB of 1 indicating a read from the part, and LSB

of 0 indicating a write to the part. The subsequent byte,

or bytes, is data from/to the specified register address.

See Figure 8 for an example of a detailed write sequence,

and Figure 9 for a read sequence.

Figure 10 shows an example of two write communication

bursts. The first byte of the first burst sent from the serial

busmasteronSDIcontainsthedestinationregisteraddress

A6 A5 A4 A3 A2

7-BIT REGISTER ADDRESS

Hi-Z

MASTER–CS

MASTER–SCLK

MASTER–SDI

LTC6948–SD0

A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0

8 BITS OF DATA

0 = WRITE

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16 CLOCKS

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