ADF5356

Data Sheet

Rev. 0 | Page 2 of 38

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications....................................................................................... 1

 

General Description ......................................................................... 1

 

Functional Block Diagram .............................................................. 1

 

Revision History ............................................................................... 2

 

Specifications..................................................................................... 3

 

Timing Characteristics ................................................................ 6

 

Absolute Maximum Ratings............................................................ 7

 

Thermal Resistance ...................................................................... 7

 

Transistor Count........................................................................... 7

 

ESD Caution.................................................................................. 7

 

Pin Configuration and Function Descriptions............................. 8

 

Typical Performance Characteristics ........................................... 10

 

Theory of Operation ...................................................................... 15

 

Reference Input Section............................................................. 15

 

RF N Divider ............................................................................... 15

 

Phase Frequency Detector (PFD) and Charge Pump............ 16

 

MUXOUT and Lock Detect...................................................... 16

 

Input Shift Registers ................................................................... 16

 

Program Modes .......................................................................... 17

 

VCO.............................................................................................. 17

 

Output Stage................................................................................ 17

 

Register Maps .................................................................................. 19

 

Register 0 ..................................................................................... 21

 

Register 1 ..................................................................................... 22

 

Register 2 ..................................................................................... 22

 

Register 3 ..................................................................................... 23

 

Register 4 ..................................................................................... 24

 

Register 5 ..................................................................................... 25

 

Register 6 ..................................................................................... 26

 

Register 7 ..................................................................................... 28

 

Register 8 ..................................................................................... 29

 

Register 9 ..................................................................................... 29

 

Register 10 ................................................................................... 30

 

Register 11 ................................................................................... 31

 

Register 12 ................................................................................... 31

 

Register 13 ................................................................................... 32

 

Register Initialization Sequence ............................................... 32

 

Frequency Update Sequence..................................................... 33

 

RF Synthesizer—A Worked Example ...................................... 33

 

Reference Doubler and Reference Divider ............................. 34

 

Spurious Optimization and Fast Lock..................................... 34

 

Optimizing Jitter......................................................................... 34

 

Spur Mechanisms ....................................................................... 34

 

PLL Lock Time ........................................................................... 34

 

Applications Information .............................................................. 36

 

Power Supplies ............................................................................ 36

 

PCB Design Guidelines for a Chip Scale Package ................. 36

 

Output Matching ........................................................................ 37

 

Outline Dimensions ....................................................................... 38

 

Ordering Guide .......................................................................... 38

 

REVISION HISTORY

8/2017—Revision 0: Initial Version