AD9833

Data Sheet

Rev. F | Page 16 of 21

RESET FUNCTION

The reset function resets appropriate internal registers to 0 to

provide an analog output of midscale. Reset does not reset the

phase, frequency, or control registers. When the AD9833 is

powered up, the part should be reset. To reset the AD9833, set

the reset bit to 1. To take the part out of reset, set the bit to 0. A

signal appears at the DAC to output eight MCLK cycles after

reset is set to 0.

Table 13. Applying the Reset Function

Reset Bit

Result

0

No reset applied

1

Internal registers reset

SLEEP FUNCTION

Sections of the AD9833 that are not in use can be powered

down to minimize power consumption. This is done using the

sleep function. The parts of the chip that can be powered down

are the internal clock and the DAC. The bits required for the

sleep function are outlined in Table 14.

Table 14. Applying the Sleep Function

SLEEP1 Bit

SLEEP12 Bit

Result

0

0

No power-down

0

1

DAC powered down

1

0

Internal clock disabled

1

1

Both the DAC powered down

and the internal clock disabled

DAC Powered Down

This is useful when the AD9833 is used to output the MSB

of the DAC data only. In this case, the DAC is not required;

therefore, it can be powered down to reduce power

consumption.

Internal Clock Disabled

When the internal clock of the AD9833 is disabled, the DAC

output remains at its present value because the NCO is no

longer accumulating. New frequency, phase, and control words

can be written to the part when the SLEEP1 control bit is active.

The synchronizing clock is still active, which means that the

selected frequency and phase registers can also be changed

using the control bits. Setting the SLEEP1 bit to 0 enables the

MCLK. Any changes made to the registers while SLEEP1 is

active will be seen at the output after a latency period.

VOUT PIN

The AD9833 offers a variety of outputs from the chip, all of which

are available from the VOUT pin. The choice of outputs is the

MSB of the DAC data, a sinusoidal output, or a triangle output.

The OPBITEN (D5) and mode (D1) bits in the control register

are used to decide which output is available from the AD9833.

MSB of the DAC Data

The MSB of the DAC data can be output from the AD9833. By

setting the OPBITEN (D5) control bit to 1, the MSB of the DAC

data is available at the VOUT pin. This is useful as a coarse clock

source. This square wave can also be divided by 2 before being

output. The DIV2 (D3) bit in the control register controls the

frequency of this output from the VOUT pin.

Sinusoidal Output

The SIN ROM is used to convert the phase information from

the frequency and phase registers into amplitude information

that results in a sinusoidal signal at the output. To have a sinusoidal

output from the VOUT pin, set the mode (D1) bit to 0 and the

OPBITEN (D5) bit to 0.

Triangle Output

The SIN ROM can be bypassed so that the truncated digital

output from the NCO is sent to the DAC. In this case, the

output is no longer sinusoidal. The DAC will produce a 10-bit

linear triangular function. To have a triangle output from the

VOUT pin, set the mode (D1) bit = 1.

Note that the SLEEP12 bit must be 0 (that is, the DAC is enabled)

when using this pin.

Table 15. Outputs from the VOUT Pin

OPBITEN Bit

Mode Bit

DIV2 Bit

VOUT Pin

0

0

Sinusoid

0

1

Triangle

1

0

0

DAC data MSB/2

1

0

1

DAC data MSB

1

1

Reserved

1

X = don’t care.

2π

4π

6π

Figure 25. Triangle Output