CPC5902GS datasheet(8/14 Pages) IXYS

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INTEGRATED CIRCUITS DIVISION

CPC5902

www.ixysic.com

R03

Functional Description

3.1 Overview

The CPC5902 combines the features of multiple logic

optoisolators and an I2C bus repeater in a single 8-pin

package. It offers excellent isolation (3750Vrms) and

speed sufficient to support I2C Fast-mode at 400kbps.

It bidirectionally buffers the two I2C signals across the

isolation barrier, and supports I2C clock stretching. If

different supply voltage levels are used at each side,

then the part, in conjunction with its external pullup

resistors, will perform logic level translation for VDD

between 2.7V and 5.5V at either side.

The CPC5902, like available non-galvanically isolating

I2C bus repeaters, has a full drive side and a limited

drive side. It uses a voltage-limited output driver and a

lower VTHRESHOLD (VIL) at the Side B IO. The

voltage-limited Side B output driver can not output a

VOL level below an internally set voltage limit. This is

necessary to ensure that the CPC5902 cannot drive

its own IOB input to a level it accepts as a logic low,

which would cause I2C bus contention. The parts are

specified with a minimum VOL-VIL margin of 25mV at

minimum VDDB, and exhibit a proportionately larger

self-drive margin with larger VDDB.

The Side A drivers are Fast-mode, full strength (6mA)

over the full VDDA range, and the input thresholds are

specified to be Fast-mode compliant; thus Side A will

drive up to the full 400pF Fast-mode CLOAD and is

allowed to drive its own input to a logic low. Devices

meeting the I2C specification are easily able to drive

the IO nodes below the CPC5902’s lower VIL

(0.2VDDB) threshold at the Side B inputs, and will

correctly accept the CPC5902 Side B driven data,

thereby enabling Side B bidirectional communication

at up to 3mA of load current over the full VDDB range.

Over the entire VDDx range, Side A is fully I

Fast-mode compliant while Side B is I2C

Standard-mode compliant. It is important to note that

Side B can be operated at the Fast-mode date rate

when the capacitive loading on the bus is kept at

200pF or less, however when VDDB > 4.5V, Side B is

also Fast-mode compliant with up to 400pF capacitive

IO pullup resistors are required on both sides of the

barrier. At the Side B inputs, resistor values should be

chosen for Standard-mode 3mA pullup current (for

operation independent of VDDB). Pullups chosen for

Fast-mode drivers (up to 6mA) can be used at Side A

with no loss of noise margin.

Applying a pulse at a Side B input inherently involves

the use of some of the output driver circuits at that I/O.

In a manner similar to the I2C clock stretching feature,

once an asserted signal is determined to be valid, it is

stretched until its proper transmission through the

optics has been verified. This insures that there will be

no extra edges generated at either side due to optic

delays. If a Side B asserted-low pulse is long enough

to be accepted and passed to Side A, then the flip-flop

at Side B is set and remains set until the signal returns

through the optics from Side A.

In operation, a valid asserted pulse of less than 80ns

applied at Side B appears at Side A after a delay

largely determined by the low-pass filter delay (tFIL)

and the optics delay (tOPHL_BA). After this initial delay

the Side A driver is activated and a logic low is

asserted at time:

tSTARTA = tFIL + tOPHL_BA

That assertion is returned across the optics to Side B

after a delay largely determined by tOPHL_AB. Upon

arriving at Side B, the flip-flop is cleared, and the

deassertion is sent through the optics to Side A,

arriving at the Side A output after a delay largely

determined by tOPLH_BA at time:

tENDA = tFIL + tOPHL_BA + tOPHL_AB + tOPLH_BA

Thus a valid Side B pulse having a width less than

80ns is stretched at Side A to a typical width of 125ns.

The duration of the pulse width output onto the Side A

bus is given by:

tPWA_min = (tOPHL_AB + tOPLH_BA)

When Side A is deasserted, the output rises at a slew

rate determined by the RC load on IOA, and passes

the logic threshold after time tSLEWA. The deasserted

(logic HIGH) input propagates through the optics and

deasserts the Side B output after a delay largely

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