4

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PS8626D

05/11/05

PI6C4120x

LVCMOS to LVPECL Driver

s

t

u

p

n

Is

t

u

p

t

u

O

N

E

_

K

L

CL

E

S

_

K

L

Ce

c

r

u

o

S

d

e

t

c

e

l

e

S*

3

Q

u

r

h

t

0

Q*

3

Q

n

u

r

h

t

0

Q

n

00

0

K

L

CW

O

L

;

d

e

l

b

a

s

i

DH

G

I

H

;

d

e

l

b

a

s

i

D

01

1

K

L

CW

O

L

;

d

e

l

b

a

s

i

DH

G

I

H

;

d

e

l

b

a

s

i

D

10

0

K

L

Cd

e

l

b

a

n

Ed

e

l

b

a

n

E

11

1

K

L

Cd

e

l

b

a

n

Ed

e

l

b

a

n

E

Table 3a. Control Input Function Table

After CLK_EN switches, the clock outputs are disabled or enabled following

a rising and falling input clock edge as shown in figure1. In the active mode, the state

of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3b.

Disabled

Enabled

CLK0, CLK1

CLK_EN

nQ0 - nQ3*

Q0 - Q3*

Figure 1. CLK_EN Timing Diagram

Table 3b. Clock Input Function Table

s

t

u

p

n

Is

t

u

p

t

u

O

1

K

L

C

r

o

0

K

L

C*

3

Q

u

r

h

t

0

Q*

3

Q

n

u

r

h

t

0

Q

n

0W

O

LH

G

I

H

1H

G

I

HW

O

L

Note:

*PI6C41204 and PI6C41204A have four differential outputs. Q0 through Q3 and nQ0 through nQ3.

PI6C41202 has two differential outputs. Q0 through Q1 and nQ0 through nQ1.