November 22, 2004

19

Philips Semiconductors

Preliminary specification

Universal LCD driver

for low multiplex rates

PCF8562

7

line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when

connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

In chip-on-glass applications where the track resistance from the SDA pad to the system SDA line can be significant, a

potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is therefore

necessary to minimize the track resistance from the SDA pad to the system SDA line to guarantee a valid LOW-level

during the acknowledge cycle.

7.1

Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period

of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.12).

7.2

Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the

clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH

is defined as the STOP condition (P), (see Fig.13).

7.3

System configuration

A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls

the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’, (see Fig.14).

7.4

Acknowledge

The number of data bytes that can be transferred from transmitter to receiver between the START and STOP conditions

is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal on the

bus that is asserted by the transmitter during which time the master generates an extra acknowledge related clock pulse.

An addressed slave receiver must generate an acknowledge after receiving each byte. Also a master receiver must

generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. The

acknowledging device must pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into

consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the

last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the

master to generate a STOP condition (see Fig.15).

7.5

master receiver. The only data output from the PCF8562 are the acknowledge signals of the selected devices. Device

7.6

Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL

lines.

7.7

slave address that a PCF8562 will respond to is defined by the level tied to its SA0 input. The PCF8562 is a write-only

device and will not respond to a read access.