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CY29946AXC датащи(PDF) 3 Page - Cypress Semiconductor

номер детали CY29946AXC
подробное описание детали  2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer
PDF  6 Pages
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY29946AXC датащи(HTML) 3 Page - Cypress Semiconductor

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CY29946
Document #: 38-07286 Rev. *E
Page 3 of 6
Absolute Maximum Conditions[2]
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature: ................................ –40°C to +85°C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ...........................................± 20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD .
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50
Ω (or 50Ω to V
DD/2) transmission lines.
5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6. Outputs driving 50
Ω transmission lines.
7. 50% input duty cycle.
8. See Figure 1.
9. Part-to-Part skew at a given temperature and voltage.
DC Electrical Specifications: VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
VSS
0.8
V
VIH
Input High Voltage
2.0
VDD
V
IIL
Input Low Current[3]
–100
µA
IIH
Input High Current[3]
100
µA
VOL
Output Low Voltage[4]
IOL = 20 mA
0.4
V
VOH
Output High Voltage[4]
IOH = –20 mA, VDD = 3.3V
2.5
V
IOH = –20 mA, VDD = 2.5V
1.8
IDDQ
Quiescent Supply Current
5
7
mA
IDD
Dynamic Supply Current
VDD = 3.3V, Outputs @ 100 MHz, CL = 30 pF
130
mA
VDD = 3.3V, Outputs @ 160 MHz, CL = 30 pF
225
VDD = 2.5V, Outputs @ 100 MHz, CL = 30 pF
95
VDD = 2.5V, Outputs @ 160 MHz, CL = 30 pF
160
ZOut
Output Impedance
VDD = 3.3V
12
15
18
W
VDD = 2.5V
14
18
22
Cin
Input Capacitance
4pF
AC Electrical Specifications VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range
[5]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Input Frequency[6]
VDD = 3.3V
200
MHz
VDD = 2.5V
170
Tpd
TTL_CLK To Q Delay[6]
5.0
11.5
ns
FoutDC
Output Duty Cycle[6, 7]
Measured at VDD/2
45
55
%
tpZL, tpZH
Output enable time (all outputs)
2
10
ns
tpLZ, tpHZ
Output disable time (all outputs)
2
10
ns
Tskew
Output-to-Output Skew[6, 8]
150
250
ps
Tskew(pp)
Part-to-Part Skew[9]
2.0
4.5
ns
Tr/Tf
Output Clocks Rise/Fall Time[8]
0.8V to 2.0V,
VDD = 3.3V
0.10
1.0
ns
0.6V to 1.8V,
VDD = 2.5V
0.10
1.3



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