ICS726A

12 TO 36 MHZ 6TSOT VCXO

VCXO

IDT® 12 TO 36 MHZ 6TSOT VCXO

3

ICS726A

REV E 021312

The third overtone mode of the crystal and all spurs must be

>100 ppm distant from the 3x fundamental resonance

measured with a physical load of 8.6pF.

The external crystal must be connected as close to the chip

as possible and should be on the same side of the PCB as

the ICS726A. There should be no vias between the crystal

pins and the X1 and X2 device pins. There should be no

signal traces underneath or close to the crystal. See

application note MAN05.

Crystal Tuning Load Capacitors

The crystal traces should include pads for small fixed

capacitors, one between X1 and ground, and another

between X2 and ground. The need for these capacitors is

determined at system prototype evaluation, and is

influenced by the particular crystal used (manufacture and

frequency) and by PCB layout. The typical required

capacitor value is 1 to 4 pF.

To determine the value of the crystal capacitors:

1. Connect VDD of the ICS726A to 3.3 V. Connect pin 5of

the ICS726A to the second power supply. Adjust thevoltage

on pin 5 to 0V. Measure and record the frequency ofthe CLK

2. Adjust the voltage on pin 5 to 3.3 V. Measure and record

measured.

If the centering error is less than ±25 ppm, no adjustment is

needed. If the centering error is more than 25 ppm negative,

the PC board has excessive stray capacitance and a new

PCB layout should be considered to reduce stray

capacitance. (Alternately, the crystal may be re-specified to

a higher load capacitance. Contact IDT for details.) If the

centering error is more than 25 ppm positive, add identical

fixed centering capacitors from each crystal pin to ground.

The value for each of these caps (in pF) is given by:

= 2 x (centering error)/ (trim sensitivity)

Trim sensitivity is a parameter which can be supplied by your

crystal vendor or calculated using the following formula: