AD9542BCPZ datasheet(1/61 Pages) AD

номер детали	AD9542BCPZ

подробное описание детали	Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator

PDF	61 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

Logo

1 / 61 page

Quad Input, Five-Output, Dual DPLL

Synchronizer and Adaptive Clock Translator

Data Sheet

AD9542

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

FEATURES

Dual DPLL synchronizes 2 kHz to 750 MHz physical layer

clocks providing frequency translation with jitter cleaning

of noisy references

Complies with ITU-T G.8262 and Telcordia GR-253

Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823,

G.824, and G.825

Continuous frequency monitoring and reference validation

for frequency deviation as low as 50 ppb

Both DPLLs feature a 24-bit fractional divider with 24-bit

programmable modulus

Programmable digital loop filter bandwidth: 10−4 Hz to 1850 Hz

Automatic and manual holdover and reference switchover,

providing zero delay, hitless, or phase buildout operation

Programmable priority-based reference switching with

manual, automatic revertive, and automatic nonrevertive

modes supported

5 pairs of clock output pins with each pair useable as

differential LVDS/HCSL/CML or as 2 single-ended outputs

(1 Hz to 500 MHz)

2 differential or 4 single-ended input references

Crosspoint mux interconnects reference inputs to PLLs

Supports embedded (modulated) input/output clock signals

Fast DPLL locking modes

Provides internal capability to combine the low phase noise

of a crystal resonator or crystal oscillator with the

frequency stability and accuracy of a TCXO or OCXO

External EEPROM support for autonomous initialization

Single 1.8 V power supply operation with internal regulation

Built in temperature monitor/alarm and temperature

compensation for enhanced zero delay performance

APPLICATIONS

SyncE jitter cleanup and synchronization

Optical transport networks (OTN), SDH, and macro and small

cell base stations

OTN mapping/demapping with jitter cleaning

Small base station clocking, including baseband and radio

Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter

cleanup, and phase transient control

JESD204B support for analog-to-digital converter (ADC) and

digital-to-analog converter (DAC) clocking

Cable infrastructures

Carrier Ethernet

GENERAL DESCRIPTION

The 10 clock outputs of the AD9542 are synchronized to any

one of up to four input references. The digital phase-locked

loops (DPLLs) reduce timing jitter associated with the external

references. The digitally controlled loop and holdover circuitry

continuously generate a low jitter output signal, even when all

reference inputs fail.

The AD9542 is available in a 48-lead LFCSP (7 mm × 7 mm)

package and operates over the −40°C to +85°C temperature

range.

Note that throughout this data sheet, multifunction pins, such

as SDO/M5, are referred to either by the entire pin name or by a

single function of the pin, for example, M5, when only that

function is relevant.

Аналогичный номер детали - AD9542BCPZ

производитель	номер детали	датащи	подробное описание детали
Analog Devices	AD9540	485Kb / 32P	655 MHz Low Jitter Clock Generator 7/04-Revision 0
	AD9540	588Kb / 32P	655 MHz Low Jitter Clock Generator 4/2018-Rev. B to Rev. C
	AD9540BCPZ	485Kb / 32P	655 MHz Low Jitter Clock Generator 7/04-Revision 0
	AD9540BCPZ	588Kb / 32P	655 MHz Low Jitter Clock Generator 4/2018-Rev. B to Rev. C
	AD9540BCPZ-REEL	485Kb / 32P	655 MHz Low Jitter Clock Generator 7/04-Revision 0

More results

Аналогичное описание - AD9542BCPZ

производитель	номер детали	датащи	подробное описание детали
Analog Devices	AD9547	1Mb / 104P	Dual/Quad Input Network Clock Generator/Synchronizer REV. 0
	AD9559BCPZ	1Mb / 120P	Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator REV. 0
	AD9543	1Mb / 66P	Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner 10/2017-Revision 0
	AD9544	1Mb / 62P	Quad Input, 10-Output, Dual DPLL, 1 pps Synchronizer and Jitter Cleaner 10/2017-Revision 0
	AD9545	2Mb / 157P	Quad Input, 10-Output, Dual DPLL/IEEE 1588 1 pps Synchronizer and Jitter Cleaner 4/2018-Rev. 0 to Rev. A
	AD9547	1Mb / 106P	Dual/Quad Input Network Clock Generator/Synchronizer 11/14-Rev. F to Rev. G
	AD9554	1Mb / 116P	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator 3/2017-Rev. C to Rev. D
	AD9554-1	927Kb / 99P	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator 3/2017-Rev. B to Rev. C
	AD9557	1Mb / 95P	Dual Input Multiservice Line Card Adaptive Clock Translator 9/2016-Rev. B to Rev. C
	AD9546	2Mb / 205P	Dual DPLL Digitized Clock Synchronizer 10/2020-Revision 0

More results

AD9542BCPZ датащи(PDF) 1 Page - Analog Devices

AD9542BCPZ датащи(HTML) 1 Page - Analog Devices

Аналогичный номер детали - AD9542BCPZ

Аналогичное описание - AD9542BCPZ

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

датащи скачать

ссылки URL