AD9523 datasheet(19/60 Pages) AD

19 / 60 page

Data Sheet

AD9523

Rev. D | Page 19 of 60

THEORY OF OPERATION

DETAILED BLOCK DIAGRAM

CHARGE

PUMP

×2

÷D1

VCXO

SWITCH-

OVER

CONTROL

÷M1

3.6GHz

4.0GHz

OUT13

OUT12

OUT11

OUT10

OUT9

OUT8

OUT7

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

OUT0

OUT13

OUT12

OUT11

OUT10

OUT9

OUT8

OUT7

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

OUT0

STATUS MONITOR

LOCK DETECT/

SERIAL PORT

ADDRESS

CONTROL

INTERFACE

(SPI AND I 2C)

SCLK/SCL

SDO

SDIO/SDA

÷N2

PLL2

LDO_PLL2

LOOP

FILTER

TO SYNC

LOOP

FILTER

CHARGE

PUMP

PLL1

LOCK

DETECT

LOCK

DETECT

ZD_IN

RESET

SYNC

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

÷D

Δt

EDGE

SYNC

SIGNAL

PLL1_OUT

VDD1.8_OUT[x:y]

REFA

REFB

AD9523

REF_SEL

STATUS0/

SP0

STATUS1/

SP1

EEPROM

EEPROM_SEL

LF2_EXT_CA P

LF1_EXT_CA P

REF_TEST

OSC_CTRL

OSC_IN

÷R

÷N1

LDO_PLL1

LDO_VCO

VDD3_OUT[x:y]

VDD3_PLL1

VDD3_PLL2

VCO

÷R

Figure 22. Top Level Diagram

OVERVIEW

The AD9523 is a clock generator that employs integer-N-based

phase-locked loops (PLL). The device architecture consists of two

cascaded PLL stages. The first stage, PLL1, consists of an integer

division PLL that uses an external voltage-controlled crystal

oscillator (VCXO) of up to 250 MHz. PLL1 has a narrow-loop

bandwidth that provides initial jitter cleanup of the input reference

signal. The second stage, PLL2, is a frequency multiplying PLL

that translates the first stage output frequency to a range of 3.6 GHz

to 4.0 GHz. PLL2 incorporates an integer-based feedback divider

that enables integer frequency multiplication. Programmable

integer dividers (1 to 1024) follow PLL2, establishing a final

output frequency of 1 GHz or less.

The AD9523 includes reference signal processing blocks that

enable a smooth switching transition between two reference

inputs. This circuitry automatically detects the presence of the

reference input signals. If only one input is present, the device

uses it as the active reference. If both are present, one becomes

the active reference and the other becomes the backup reference.

If the active reference fails, the circuitry automatically switches

to the backup reference (if available), making it the new active

reference. A register setting determines what action to take if

the failed reference is once again available: either stay on

Reference B or revert to Reference A. If neither reference can

be used, the AD9523 supports a holdover mode. A reference

select pin (REF_SEL, Pin 16) is available to manually select

which input reference is active (see Table 43). The accuracy of

the holdover is dependent on the external VCXO frequency

stability at half supply voltage.

Any of the divider settings are programmable via the serial

programming port, enabling a wide range of input/output

frequency ratios under program control. The dividers also

include a programmable delay to adjust the timing of the output

signals, if required.

The 14 outputs are compatible with LVPECL, LVDS, HSTL, and

1.8 V CMOS logic levels (see the Input/Output Termination

Recommendations section). All differential output logic settings

require a single 100 Ω differential termination.

The loop filters of each PLL are integrated and programmable.

Only a single external capacitor for each of the two PLL loop

filters is required.

The AD9523 operates over the extended industrial temperature

range of −40°C to +85°C.

AD9523 датащи(PDF) 19 Page - Analog Devices

AD9523 датащи(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL