поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

LTC6953 датащи(PDF) 43 Page - Analog Devices

номер детали LTC6953
подробное описание детали  Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B Support
PDF  56 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

LTC6953 датащи(HTML) 43 Page - Analog Devices

Back Button LTC6953 Datasheet HTML 39Page - Analog Devices LTC6953 Datasheet HTML 40Page - Analog Devices LTC6953 Datasheet HTML 41Page - Analog Devices LTC6953 Datasheet HTML 42Page - Analog Devices LTC6953 Datasheet HTML 43Page - Analog Devices LTC6953 Datasheet HTML 44Page - Analog Devices LTC6953 Datasheet HTML 45Page - Analog Devices LTC6953 Datasheet HTML 46Page - Analog Devices LTC6953 Datasheet HTML 47Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 43 / 56 page
background image
LTC6953
43
Rev 0
For more information www.analog.com
Preliminary Technical Data
Advance Product Information Subject to Change
Rev PrA
APPLICATIONS INFORMATION
Figure 27. Outputs After Synchronization for the EZSync Multichip Design Example (SRQMD = 0)
Figure 28. Outputs After SYSREF Request for the EZSync Multichip Design Example (SRQMD = 1)
ADC DEVICE CLOCKS
(OUT1, 3, 5 AND 7)
FOLLOWER DRIVER
(OUT8)
SYNC PASS-THROUGH
(OUT9)
tPD
ADC SYSREFs
(MUTED OUT0, 2, 4 AND 6)
DAC DEVICE CLOCKS
(OUT4, 6, 8 AND 10)
FOLLOWER OUTPUTS
CONTROLLER OUTPUTS
DAC SYSREFs
(MUTED OUT3, 5, 7 AND 9)
FPGA SYSREF
(MUTED OUT1)
FPGA MANAGEMENT CLOCK
(OUT 2)
SYSREF VALID CLOCK EDGE
NOT SYNCHRONIZED, PHASE UNDETERMINED
6953 F27
FPGA DEVICE CLOCK
(OUT2)
INTERNAL ADC SYSREF DIVIDERS
(MUTED OUT0, 2, 4 AND 6)
INTERNAL DAC SYSREF DIVIDERS
(MUTED OUT3, 5, 7 AND 9)
INTERNAL FPGA SYSREF DIVIDER
(MUTED OUT1)
EZS_SRQ or SSRQ BIT
EZS_SRQ OR SSRQ BIT
CONTROLLER OUTPUTS
FOLLOWER OUTPUTS
6953 F28
FOLLOWER DRIVER
(OUT8)
SYSREQ PASS-THROUGH
(OUT9)
ADC DEVICE CLOCKS
(OUT1, 3, 5 AND 7)
ADC SYSREFs
(OUT0, 2, 4 AND 6)
DAC DEVICE CLOCKS
(OUT4, 6, 8 AND 10)
DAC SYSREFs
(OUT3, 5, 7 AND 9)
FPGA SYSREF
(OUT1)
FPGA DEVICE CLOCK
(OUT2)
4000MHz
FPGA MANAGEMENT CLOCK
(OUT10)
100MHz
4000MHz
125MHz
500MHz



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com