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MMPF0200 датащи(PDF) 64 Page - NXP Semiconductors |
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MMPF0200 датащи(HTML) 64 Page - NXP Semiconductors |
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64 / 114 page ![]() 64 NXP Semiconductors PF0200 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as programmed to stay “ON” or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for this. Table 78 presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output. For more detail information, Table 79 through Table 84 provide a description of all registers necessary to operate all six general purpose LDO regulators. Table 77. VGEN3/ 4/ 5/ 6 output voltage configuration Set point VGENx[3:0] VGENx output (V) 00000 1.80 10001 1.90 20010 2.00 30011 2.10 40100 2.20 50101 2.30 60110 2.40 70111 2.50 81000 2.60 91001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 14 1110 3.20 15 1111 3.30 Table 78. LDO control VGENxEN VGENxLPWR VGENxSTBY STANDBY(55) VGENxOUT 0X X X Off 10 0 X On 1 1 0 X Low Power 1X 1 0 On 10 1 1 Off 1 1 1 1 Low Power Notes 55. STANDBY refers to a Standby event as described earlier. |
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