FUSB302BVMPX datasheet(12/32 Pages) ONSEMI

12 / 32 page

FUSB302B

www.onsemi.com

PD Send

The FUSB302B implements part of the PD protocol layer

for sending packets in an autonomous fashion.

Figure 13.

Hard

Reset

Soft Reset

Automatic

Sending Retries

PD Packet

Sent

PD Automatic Sending Retries

If GoodCRC packet is not received and AUTO_RETRY

is set, then a retry of the same message that was in the

TxFIFO written by the processor is executed within tRetry

and that is repeated for NRETRY times.

PD Send Soft Reset

If the correct GoodCRC packet is still not received for all

retries then I_RETRYFAIL interrupt is triggered and if

AUTO_SOFT_RESET is set, then a Soft Reset packet is

created (MessageID is set to 0 and the processor upon

servicing

I_RETRYFAIL

would

set

the

true

MessageIDCounter to 0.

If this Soft Reset is sent successfully where a GoodCRC

control packet is received with a MessageID = 0 then

I_TXSENT interrupt occurs.

If not, this Soft Reset packet is retried NRETRIES times

(MessageID is always 0 for all retries) if a GoodCRC

acknowledge packet is not received with CRCReceiveTimer

expiring (tReceive of 1.1 ms max). If all retries fail, then

I_SOFTFAIL interrupt is triggered.

PD Send Hard Reset

If all retries of the soft reset packet fail and if

AUTO_HARD_RESET is set, then a hard reset ordered set

is sent by loading up the TxFIFO with RESET1, RESET1,

RESET1, RESET2 and sending a hard reset. Note only one

hard reset is sent since the typical retry mechanism doesn’t

apply.

The

processor’s

policy

engine

firmware

responsible for retrying the hard reset if it doesn’t receive the

required response.

Flush Rx-FIFO with BIST (Built-In Self Test) Test Data

During PD compliance testing, BIST test packets are used

to test physical layer of the PD interface such as, frequency

derivation, Amplitude measure and etc. The one BIST test

data packet has 7 data objects (28byte data), header and

CRC, but the message ID doesn’t change, the packet should

be ignored and not acted on by the PD policy engine. The PD

protocol layer does need to send a GoodCRC message back

after every packet. The BIST data can arrive continuously

from a tester, which could cause the FUSB302B Rx FIFO to

overflow and the PD protocol layer to stop sending

GoodCRC messages unless the FIFO is read or cleared

quickly. The FUSB302B has a special register bit in the I2C

registers, bit[5] of address 0x09, that when the bit is set, all

the data received next will be flushed from the RxFIFO

automatically and the PD protocol layer will keep sending

GoodCRC messages back. Once BIST test is done, tester

sends HardReset, so with the HardReset, processor has to

write the bit back to disable. Also, if the bit can be

de-selected anytime, then the coming packet has to be

managed by protocol layer and policy engine.

I2C INTERFACE

The FUSB302B includes a full I2C slave controller. The

I2C slave fully complies with the I2C specification version

6 requieremnts. This block is designed for Fast Mode Plus

traffic up to 1 MHz SCL operation.

The TOGGLE features allow for very low power

operation with slow clocking thus may not be fully

compliant to the 1 MHz operation. Examples of an I2C write

and read sequence are shown in Figure 14 and Figure 15

respectively.

Figure 14. I2C Write Example

SWR A

A P

Note: Single Byte read is initiated by Master with P immediately following first data byte

8bits

Write Data K+2

Slave Address

Write Data

Write Data K+1

Write Data K+N−1

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