FUSB301A

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3

PIN DESCRIPTIONS

Pin #

Name

Type

Description

USB Type−C Connector Interface

1, 2

CC1, CC2

I/O

Type−C Configuration Channel

4

VBUS

Input

VBUS input pin for attach and detach detection

10

GND

Ground

Ground

Power Interface

12

VDD

Power

Input Supply Voltage

Signal Interface

8

SCL

Input

7

SDA

Open−Drain

I/O

6

INT_N

Open−Drain

Output

Active LOW open drain interrupt output used to prompt the processor

9

ID

Open−Drain

Output

Used to Identify if connected device is Source or Sink. The ID Pin

can be used to interface with USB 2.0 Input on the processor.

5

I2CADDR

Input

Used to change bit 3 of the I2C address so that multiple addresses

can be used in a system where two device addresses conflict

3

NC1

NC

No Connect − Tie to Ground or Float

11

NC2

NC

No Connect − Tie to Ground or Float

Dead Battery

If power is not applied to FUSB301A and it is attached to

a Source device, then the Source would pull up the CC line

connected through the cable. The FUSB301A in response

would turn on the pull−down that will bring the CC voltage

to a range that the Source can detect an attach and turn on

VBUS.

Power Up, Initialization and Reset, Interrupt Operation

When power is first applied, the FUSB301A will power

up in Sink mode with all interrupts masked. The local

processor must configure the FUSB301A to the desired

mode and clear the global interrupt mask bit, INT_MASK.

The INT_N pin is an active low, open drain output. This pin

indicates to the host processor that an interrupt has occurred

in the FUSB301A which needs attention. The INT_N pin is

in a high impedance state by default after power−up or

device reset, and the global interrupt mask (INT_MASK in

Control register) is set. After INT_MASK bit is cleared by

the local processor, the INT_N pin stays high impedance in

preparation of future interrupts. When an interruptible event

occurs, INT_N is driven LOW and is in a high impedance

state again when the processor clears the interrupt by reading

the interrupt registers. Subsequent to the initial power up or

reset; if the processor writes a “1” to global interrupt mask

bit when the system is already powered up, the INT_N pin

stays in a high impedance state and ignores all interrupts

until the global interrupt mask bit is cleared. If an event

happens that would ordinarily cause an interrupt when the

global interrupt mask bit is set, the INT_N pin goes LOW

when the global interrupt mask is cleared.

Table 1. ID PIN TRUTH TABLE

Type Register (h12, bit 4)

Description

ID

SINK = b0

SINK Not Detected

Hi−Z (default)

SINK = b1

SINK Detected

Low

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min.

Max.

Unit

−0.5

6.0

V

VBUS Supply Voltage

−0.5

28

V

CC pins when configured as Host, Device or Dual Role Port

−0.5

6.0

V

Storage Temperature Range

−65

+150

°C