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WM8988 датащи(PDF) 21 Page - Cirrus Logic

номер детали WM8988
подробное описание детали  Stereo CODEC for Portable Audio Applications
PDF  58 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8988 датащи(HTML) 21 Page - Cirrus Logic

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WM8988
Rev 4.2
21
ADC DIGITAL FILTER
The ADC filters perform true 24-bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital
filter path is illustrated in Figure 8.
FROM ADC
DIGITAL
HPF
DIGITAL
FILTER
TO DIGITAL
AUDIO
INTERFACE
DIGITAL
DECIMATOR
ADCHPD
Figure 8 ADC Digital Filter
The ADC digital filters contain a digital high-pass filter, selectable via software control. The high-pass
filter response is detailed in the Digital Filter Characteristics section. When the high-pass filter is
enabled the DC offset is continuously calculated and subtracted from the input signal. By setting
HPOR, the last calculated DC offset value is stored when the high-pass filter is disabled and will
continue to be subtracted from the input signal. If the DC offset is changed, the stored and subtracted
value will not change unless the high-pass filter is enabled. This feature can be used for calibration
purposes. In addition the high-pass filter may be enabled separately on the left and right channels
(see Table 11).
The output data format can be programmed by the user to accommodate stereo or monophonic
recording on both inputs.
The polarity of the output signal can also be changed under software
control. The software control is shown in Table 10.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
ADC and DAC
Control
6:5
ADCPOL
[1:0]
00
00 = Polarity not inverted
01 = L polarity invert
10 = R polarity invert
11 = L and R polarity invert
4
HPOR
0
Store dc offset when high-pass
filter disabled
1 = store offset
0 = clear offset
0
ADCHPD
0
ADCHPD and HPFLREN together
determine high-pass filter
behaviour (see Table 11)
R27 (1Bh)
5
HPFLREN
0
Table 10 ADC Signal Path Control
HPFLREN
ADCHPD
LEFT CHANNEL
RIGHT CHANNEL
0
0
HPF ON
HPF ON
0
1
HPF OFF
HPF OFF
1
0
HPF ON
HPF OFF
1
1
HPF OFF
HPF ON
Table 11 ADC High Pass Filter Modes



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