| поискавой системы для электроныых деталей |
|
PEX8796 датащи(PDF) 4 Page - PLX Technology |
|
|
|||||||||||||||||||||||||||||
PEX8796 датащи(HTML) 4 Page - PLX Technology |
|
4 / 5 page ![]() PEX8796, PCI Express Gen3 Switch, 96 Lanes, 24 Ports © PLX Technology, www.plxtech.com Page 4 of 5 24July12; v1.2 Multi-Host Systems In multi-host mode, the PEX8796 can support up to four hosts at once. By creating four virtual switches, the PEX8796 allows four hosts to fan-out to their respective endpoints. This reduces the number of switches required for fan-out, saving precious board space and power. In Figure 7, the PEX8796 is being shared by four different CPU cores (hosts) on three servers, with each CPU core running its own applications (I/Os). The PEX8796 assigns the endpoints to the appropriate host and isolates them from the other hosts. In Figure 7, the endpoints are assigned to the CPU core of the same color. Figure 7. Multi-Host System High-End Graphics Systems The PEX8796’s 96 lanes can come in handy for high- end graphics systems, such as high-resolution gaming and medical imaging applications, employing two or more GPUs alongside multiple endpoints. Figure 8a shows a dual-graphics system where the PEX8796 is being used to fan-out to two GPUs using x16 links and numerous (up to 16) endpoints using x4 and x8 links. Figure 8b, shows an ultra-gaming system using the PEX8796 to fan-out to four GPUs via x16 links. In both examples, two x16 upstream ports are being used. Using PEX8796’s multi-host capabilities, two separate virtual hierarchies can be created, assigning GPUs & endpoints to a particular CPU core via the x16 upstream ports. Host Failover The PEX8796 can also be utilized in applications where host failover is required. In the below application (Figure 9), two hosts may be active simultaneously and controlling their own domains while exchange status information through doorbell registers or I 2C interface. The devices can be programmed to trigger fail-over if the heartbeat information is not provided. In the event of a failure, the surviving device will reset the endpoints connected to the failing CPU and enumerate them in its own domain without impacting the operation of endpoints already in its domain. Figure 9. Host Fail-Over I/O I/O Chip Set CPU Chip Set CPU I/O I/O Chip Set CPU I/O I/O PEX 8796 I/O I/O Chip Set CPU CPU CPU CPU CPU x8 x4 & x8 Chipset PEX 8796 CPU CPU CPU CPU x8 Chipset PEX 8796 x8s |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |