PEX8764, PCI Express Gen3 Switch, 64 Lanes, 16 Ports

© PLX Technology, www.plxtech.com

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07Oct13; v1.3

Highlights

o

64-lane, 16-port PCIe Gen3 switch

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Integrated 8.0 GT/s SerDes

o

o

Typical Power: 1 . Watts

o Standards Compliant

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PCI Express Base Specification, r3.0

(compatible w/ PCIe r1.0a/1.1 & 2.0)

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PCI Power Management Spec, r1.2

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Microsoft Windows Logo Compliant

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Supports Access Control Services

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Dynamic link-width control

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Dynamic SerDes speed control

o High Performance

 performancePAK



Multicast



Dynamic Buffer/FC Credit Pool

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Non-blocking switch fabric

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Full line rate on all ports

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Cut-Thru with 150ns max packet latency

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2KB Max Payload Size

o Multi-Host & Fail-Over Support

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2 Configurable Non-Transparent ports

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Failover with Non-Transparent port

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Up to 4 upstream/Host ports with 1+1 or

N+1 failover to other upstream ports

o Quality of Service (QoS)

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Traffic Class Queuing

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Eight traffic classes per port

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Weighted round-robin source

port arbitration

o Reliability, Availability, Serviceability

 visionPAK



Per Port Performance Monitoring



SerDes Eye Capture



PCIe Packet Generator



Error Injection and Loopback

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Hot-Plug ports with native HP Signals

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SSC Isolation on up to 16 ports

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ECRC and Poison bit support

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Data Path parity

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Memory (RAM) Error Correction

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Advanced Error Reporting

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Port Status bits and GPIO available

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JTAG AC/DC boundary scan

The ExpressLane

switching capability enabling users to connect multiple hosts to their

respective endpoints via scalable, high bandwidth, non-blocking

interconnection to a wide variety of applications including servers, storage

systems, and communications platforms. The PEX8764 is well suited for

fan-out, aggregation, and peer-to-peer applications.

Multi-Host Architecture

The PEX8764 employs and enhanced architecture, which allows users to

configure the device in legacy single-host mode or multi-host mode with up

to four host ports capable of 1+1 (one active & one backup) or N+1 (N active

& one backup) host failover. This powerful architectural enhancement

enables users to build PCIe based systems to support high-availability,

failover, redundant and clustered systems.

High Performance & Low Packet Latency

The PEX8764 architecture supports packet cut-thru with a maximum

latency of 150ns (x16 to x16).

This, combined with large packet memory,

flexible common buffer/FC credit pool and non-blocking internal switch

architecture, provides full line rate on all ports for performance-hungry

applications such as servers and switch fabrics. The low latency enables

applications to achieve high throughput and performance. In addition to low

latency, the device supports a packet payload size of up to 2048 bytes,

enabling the user to achieve even higher throughput.

Data Integrity

The PEX8764 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction circuitry

throughout the internal data paths as packets pass through the switch.

Flexible Configuration

The PEX8764’s 16 Ports can be configured

to lane widths of x4, x8, or x16. Flexible

buffer allocation, along with the device's

flexible packet flow control,

maximizes

throughput for applications where more

traffic flows in the downstream, rather than

upstream, direction. Any port can be

designated as the upstream port, which can

be changed dynamically. Figure 1 shows

some of the PEX8764’s common port

configurations in legacy Single-Host mode.

The PEX8764 can also be configured in

Multi-Host mode where users can choose up to four ports as host/upstream

ports and assign a desired number of downstream ports to each host. In

Multi-Host mode, a virtual switch is created for each host port and its

associated downstream ports inside the device. The traffic between the ports

of a virtual switch is completely isolated from the traffic in other virtual

switches. Figure 2 illustrates some configurations of the PEX8764 in Multi-

Host mode where each ellipse represents a virtual switch inside the device.