854057AG

www.icst.com/products/hiperclocks.html

REV. A JULY 18, 2005

10

Integrated

Circuit

Systems, Inc.

ICS854057

WITH

Figure 4shows a schematic example of the ICS854057. In this

example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are

used. The decoupling capacitors should be physically located

near the power pin.

For applications not requiring the use of a differential input, both

the PCLK and nPCLK pins can be left floating. Though not

required, but for additional protection, a 1k

Ω resistor can be tied

from PCLK to ground.

All unused LVDS outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential

output pair should either be left floating or terminated.

(U1,20)

R2

680

Zo = 50

Zo = 50

VDD

VDD

VDD

R3

680

Zo = 50

Zo = 50

R5

100

R1

680

U1

ICS854057

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

20

19

18

17

VDD

PCLK0

VT0

nPCLK0

SEL1

SEL0

PCLK1

VT1

nPCLK1

GND

GND

nPCLK2

VT2

PCLK2

nQ

Q

VDD

PCLK3

VT3

nPCLK3

Zo = 50

VDD

VDD

LVDS

+

-

R4

680

R6

18

Zo = 50

VDD

VDD

VD D=2.5V

LVDS

R1

1K

LVPECL

C2

0.1u

(U1,1)

R1

1K

C1

0.1u