ADV7282AWBCPZ datasheet(21/28 Pages) AD

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Data Sheet

ADV7282A

Rev. A | Page 21 of 28

MIPI Tx OUTPUT (ADV7282A-M ONLY)

The decoder in the ADV7282A-M outputs an ITU-R BT.656

data stream. The ITU-R BT.656 data stream is connected into a

CSI-2 Tx module. Data from the CSI-2 Tx module is fed into a

D-PHY physical layer and output serially from the device.

The output of the ADV7282A-M consists of a single data

channel on the D0P and D0N lanes and a clock channel on the

CLKP and CLKN lanes.

Video data is output over the data lanes in high speed mode.

The data lanes enter low power mode during the horizontal

and vertical blanking periods.

The clock lanes clock the output video. After the ADV7282A-M

is programmed, the clock lanes exit low power mode and remain

in high speed mode until the device is reset or powered down.

The ADV7282A-M outputs video data in an 8-bit, YCrCb, 4:2:2

format. When the I2P core is disabled, the video data is output

in an interlaced format at a nominal data rate of 216 Mbps. When

the I2P core is enabled, the video data is output in a progressive

format at a nominal data rate of 432 Mbps (see the I2P Function

section for more information).

I2C PORT DESCRIPTION

The ADV7282A supports a 2-wire, I2C-compatible serial interface.

Two inputs, serial data (SDATA) and serial clock (SCLK), carry

information between the ADV7282A and the system I2C master

controller. The I2C port of the ADV7282A allows the user to set

up and configure the decoder and to read back captured VBI data.

The ADV7282A has a variety of possible I2C slave addresses and

subaddresses (see the Register Maps section). The main map of

the ADV7282A has four possible slave addresses for read and

write operations, depending on the logic level of the ALSB pin

(see Table 20).

Table 20. Main Map I2C Addresses

ALSB Pin

R/W Bit

Slave Address

0x40 (write)

0x41 (read)

0x42 (write)

0x43 (read)

The ALSB pin controls Bit 1 of the slave address. By changing

the logic level of the ALSB pin, it is possible to control two

ADV7282A devices in an application without using the same

I2C slave address. The LSB (Bit 0) specifies either a read or write

operation: Logic 1 corresponds to a read operation, and Logic 0

corresponds to a write operation.

To control the device on the bus, use the following protocol:

1. The master initiates a data transfer by establishing a start

condition, defined as a high to low transition on SDATA

while SCLK remains high, and indicates that an

address/data stream follows.

2. All peripherals respond to the start condition and shift

the next eight bits (the 7-bit address plus the R/W bit).

The bits are transferred from MSB to LSB.

3. The peripheral that recognizes the transmitted address

responds by pulling the data line low during the ninth

clock pulse; this is known as an acknowledge (ACK) bit.

4. All other devices withdraw from the bus and maintain an

idle condition. In the idle condition, the device monitors

the SDATA and SCLK lines for the start condition and the

correct transmitted address.

The R/W bit determines the direction of the data. Logic 0 on the

LSB of the first byte means that the master writes information

to the peripheral. Logic 1 on the LSB of the first byte means that

the master reads information from the peripheral.

D0P

(1 BIT)

D0N

(1 BIT)

CLKP

(1 BIT)

CLKN

(1 BIT)

ITU-R BT.656

DATA

STREAM

CSI-2

VIDEO

DECODER

D-PHY

ANALOG

VIDEO

INPUT

CSI Tx DATA

OUTPUT (8 BITS)

DATA LANE LP

SIGNALS (2 BITS)

CLOCK LANE LP

SIGNALS (2 BITS)

Figure 13. MIPI Tx Output Stage of the ADV7282A-M

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