MOTOROLA

SEMICONDUCTOR

PRODUCT BRIEF

This document contains information on a new product. Specifications and

information herein are subject to change without notice.

© MOTOROLA 2001, All Rights Reserved

MPC561PB/D

Rev. 1, December 2001

MPC561/MPC562

MPC563/MPC564

Product Brief

MPC561/MPC562 / MPC563/MPC564 RISC MCU

Including Peripheral Pin Multiplexing with

Flash and Code Compression Options

Features

The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller

family. As shown in the block diagram, they are composed of:

• High performance CPU system

— High performance core

• Single issue integer core

• Compatible with PowerPC instruction set architecture

• Precise exception model

• Floating point

• Extensive system development support

— On-chip watchpoints and breakpoints

— Program flow tracking

— Background debug mode (BDM)

— IEEE-ISTO Nexus 5001-1999 Class 3 Debug Interface

— MPC500 system interface (USIU, BBC, L2U)

— Fully static design

— Four major power saving modes

• On, doze, sleep, deep-sleep and power-down

— 32-Kbyte static RAM (CALRAM)

— 512-Kbyte flash (UC3F) on MPC563/MPC564

— General-purpose I/O support

• On address (24) and data (32) pins

• 16 GPIO in MIOS14

• Many peripheral pins can be used as GPIO when not used as primary functions

• 2.6-V outputs on external bus pins

• PPM (peripheral pin multiplexing with parallel-to-serial driver) module

• Available in package or die

— Plastic ball grid array (PBGA) packaging

Key Feature Details

MPC500 System Interface (USIU)

• System configuration and protection features:

— Periodic-interrupt timer

— Bus monitor

— Software watchdog timer

— Real-time clock (RTC)