WM8974 datasheet(68/89 Pages) CIRRUS

68 / 89 page

WM8974

Rev 4.7

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

5 (05h)

8:5

0000

Reserved

4:3

DAC_COMP

DAC companding

00=off

01=reserved

10=µ-law

11=A-law

Digital Audio

Interfaces

2:1

ADC_COMP

ADC companding

00=off

01=reserved

10=µ-law

11=A-law

Digital Audio

Interfaces

LOOPBACK

Digital loopback function

0=No loopback

1=Loopback enabled, ADC data output is fed directly

into DAC data input.

Digital Audio

Interfaces

6 (06h)

CLKSEL

Controls the source of the clock for all internal operation:

0=MCLK

1=PLL output

Digital Audio

Interfaces

7:5

MCLKDIV

010

Sets the scaling for either the MCLK or PLL clock output

(under control of CLKSEL)

000=divide by 1

001=divide by 1.5

010=divide by 2

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

Digital Audio

Interfaces

4:2

BCLKDIV

000

Configures the BCLK and FRAME output frequency, for

use when the chip is master over BCLK.

000=divide by 1 (BCLK=MCLK)

001=divide by 2 (BCLK=MCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

Digital Audio

Interfaces

Reserved

Sets the chip to be master over FRAME and BCLK

0=BCLK and FRAME clock are inputs

1=BCLK and FRAME clock are outputs generated by

the WM8974 (MASTER)

Digital Audio

Interfaces

7 (07h)

8:4

00000

Reserved

3:1

000

Approximate sample rate (configures the coefficients for

the internal digital filters):

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Audio Sample

Rates

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