 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
WM8946 датащи(PDF) 21 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8946 датащи(HTML) 21 Page - Cirrus Logic |
|
|
21 / 173 page  WM8946 Rev 4.5 21 CS (input) SCLK (input) SDA (input) tCSU tCHO tSCH tSCL tSCY tDHO tDSU Figure 8 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle) Note: The data is latched on the 32nd falling edge of SCLK after 32 bits have been clocked into the device. SCLK (input) SDOUT (output) tDL CS (input) Figure 9 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle) Test Conditions DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V, TA = +25 oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT CS ¯¯ falling edge to SCLK rising edge tCSU 40 ns SCLK falling edge to CS rising edge tCHO 10 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL 80 ns SCLK pulse width high tSCH 80 ns SDA to SCLK set-up time tDSU 40 ns SDA to SCLK hold time tDHO 10 ns Pulse width of spikes that will be suppressed tps 0 5 ns SCLK falling edge to SDOUT transition tDL 40 ns |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
