CLA100E1200KB

0.01

0.1

1

400

500

600

700

800

900

1000

0.5

1.0

1.5

0

50

100

150

1

10

100

1000

10000

0.00

0.04

0.08

0.12

0.16

0.20

0.24

I

TSM

[A]

I

T

[A]

V

t [ms]

Z

thJC

[K/W]

2

3

4 5 6 7 8 9 0

1

1

1000

10000

I

[A

t [ms]

I

T(AV)M

[A]

T

0

25

50

75 100 125 150 175

0

20

40

60

80

100

120

Fig. 1 Forward characteristics

Fig. 3 I

t [s]

Fig. 6 Max. forward current

at case temperature

Fig. 2 Surge overload current

Fig. 8 Transient thermal impedance

T

T

T

50 Hz, 80% V

RRM

T

T

V

125°C

150°C

0

25

50

75 100 125

0

40

80

120

160

200

I

P

(AV)

[W]

Fig. 7a Power dissipation versus direct output current

Fig. 7b and ambient temperature

0

50

100

150

T

dc =

1

0.5

0.4

0.33

0.17

0.08

10

100

1000

1

10

100

1000

1

10

100

1000

10000

0.1

1

10

I

V

G

[V]

4: P

t

gd

[µs]

I

typ.

Limit

T

Fig. 4 Gate trigger characteristics

Fig. 5 Gate controlled delay time

6

4

5

2

1

3

dc =

1

0.5

0.4

0.33

0.17

0.08

1: I

R

thHA

0.4

0.6

0.8

1.0

2.0

4.0

i

R

t

1

0.032

0.0110

2

0.018

0.0001

3

0.021

0.0200

4

0.034

0.3500

5

0.095

0.1400

Thyristor

IXYS reserves the right to change limits, conditions and dimensions.

20150827b

Data according to IEC 60747and per semiconductor unless otherwise specified

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