Data Sheet

ADV7613

Rev. B | Page 5 of 13

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

PLL Power Supply

29

mA

Comparator Power Supply

66

mA

LVDS Power Supply

43

mA

Configuration 3

Pseudorandom test pattern; 1920 × 1080p at 60 Hz input

resolution; 148.5 MHz pixel clock; 85°C operating temperature;

DVDD, PVDD, CVDD, and LTX_DVDD = 1.89 V; DVDDIO and

TVDD = 3.465 V; LVDS Port 1 and LVDS Port 2 used

Termination Power Supply

70

mA

Digital I/O Power Supply

15

mA

Digital Core Power Supply

147

mA

PLL Power Supply

44

mA

Comparator Power Supply

96

mA

LVDS Power Supply

88

mA

POWER-DOWN CURRENT⁴

Terminator Power Supply

327

µA

Digital I/O Power Supply

387

µA

Digital Core Power Supply

102

µA

PLL Power Supply

223

µA

Comparator Power Supply

74

µA

LVDS Power Supply

323

µA

1

Data characterized by evaluation.

2

The following pins are 5 V tolerant inputs: DDCA_SCL, DDCA_SDA, and RXA_5V.

3

The HPA_A pin is a 5 V tolerant output.

4

Data characterized by evaluation.

LVDS TRANSMITTER (OpenLDI MAPPING)

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Differential Output Voltage

247

350

454

mV

Offset Output Voltage

1.125

1.2

1.375

V

50

mV

50

mV

OpenLDI Output Rise Time

0.21 × UI

0.3 × UI

ps

OpenLDI Output Fall Time

0.21 × UI

0.3 × UI

ps

1

Measurement performed using a 100 Ω termination resistor.

2

Data characterized by evaluation, using a 100 Ω source termination resistor. UI is unit interval, that is, the bit width.

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

CLOCK AND CRYSTAL

Crystal (XTAL) Frequency

28.63636

MHz

XTAL Frequency Stability

±50

ppm

Input Clock Range (TMDS)

25

148.5

MHz

OpenLDI Output Clock Range

25

92

MHz

SCL Frequency

400

kHz

SCL Minimum Pulse Width High

600

ns

SCL Minimum Pulse Width Low

1.3

µs

Start Condition Hold Time

600

ns