Data Sheet

ADV7482

THOERY OF OPERATION

HDMI RECEIVER

The HDMI receiver supports video formats ranging from 480i

to 1080p, and display resolutions from VGA (640 × 480 at

60 Hz) to UXGA (1600 × 1200 at 60 Hz).

The HDMI receiver allows programmable equalization of the

HDMI data signals. This equalization compensates for the high

frequency losses inherent in HDMI and DVI cabling, especially

at longer lengths and higher frequencies. The receiver is capable

of equalizing for cable lengths up to 30 meters to achieve robust

receiver performance.

The HDMI interface of the ADV7482 allows for authentication

of a video receiver, decryption of encoded data at the receiver,

and renewability of that authentication during transmission, as

specified by the HDCP 1.4 protocol.

Dual extended display identification data (EDID) support is

provided via an on-chip 512-byte EDID RAM. The EDID RAM

must be programmed at power-up. It can be configured as two

256-byte EDIDs, or as a single 512-byte EDID.

The ADV7482 has a synchronization regeneration block used to

regenerate the data enable (DE) signal based on the measurement

of the video format being displayed and to filter the horizontal

and vertical synchronization signals to prevent glitches.

The HDMI receiver also supports TMDS error reduction

coding, 4-bit (TERC4) error detection, used for the detection of

corrupted HDMI packets.

The main HDMI receiver features include

•

162.0 MHz (UXGA at 24 BPP) maximum TMDS clock

frequency.

•

Integrated fully adaptive equalizer for cable lengths up to

30 meters.

•

HDCP 1.4 support.

•

Internal HDCP keys.

•

HDCP repeater support, up to 25 key selection vectors

(KSVs) supported.

•

PCM audio packet support.

•

Support for 8-channel TDM output data up to 48 kHz.

•

Repeater support.

•

Internal EDID RAM (512-byte for single mode, and

256-byte for dual mode operation).

•

Hot Plug assert output pin (HPD).

•

CEC controller.

COMPONENT PROCESSOR

The ADV7482 has one any-to-any 3 × 3 CSC matrix. The CSC

block is located in the processing path before the CP section.

CSC enables YCbCr-to-RGB and RGB-to-YCbCr conversions.

Many other standards of color space can be implemented using

the color space converter.

CP features include

•

Support for all video modes supported by the HDMI

receiver. These include 525i, 625i, 525p, 625p, 1080i, 1080p,

and display resolutions from VGA (640 × 480 at 60 Hz) to

UXGA (1600 × 1200 at 60 Hz).

•

Manual adjustments including gain (contrast), offset

(brightness), hue, and saturation.

•

Free run output mode that provides stable timing when no

video input is present.

•

Timing adjustments controls for HS/VS/DE timing.

ANALOG FRONT END

The ADV7482 AFE comprises a single high speed, 10-bit ADC

that digitizes the analog video signal before applying it to the

SDP. The AFE uses differential channels to the ADC to ensure

high performance in mixed-signal applications and to enable

differential CVBS to be connected directly to the ADV7482.

Up to eight analog inputs can be connected to the AFE. The

front end also includes an 8-channel input mux that enables

different configurations of single-ended CVBS (up to eight),

pseudo differential or fully differential CVBS (up to four), Y/C

(up to four), and YPbPr (up to two) analog inputs.

Current clamps are positioned in front of the ADC to ensure

that the video signal remains within the range of the converter.

A resistor divider network is required before each analog input

channel to ensure that the input signal is within the range of the

ADC. Figure 11 shows a typical voltage divider network for

single-ended inputs, Figure 12 shows a typical voltage divider

network for pseudo differential inputs, and Figure 13 shows a

typical voltage divider network for fully differential inputs. The

choice of the resistor divider shown in Figure 13 provides a

common-mode range of up to 4 V in fully differential CVBS

input mode. Fine clamping of the video signal is performed

downstream by digital fine clamping within the ADV7482.

Figure 11. Typical Single-Ended Input Voltage Divider Network

Figure 12. Typical Pseudo Differential Input Resistor Divider Network

AIN

ANALOG

INPUT

51Ω

24Ω

100nF

AINx

AINy

ANALOG INPUT

ANALOG INPUT

CVBS_P

CVBS_N

1.3kΩ

1.3kΩ

75Ω

430Ω

430Ω

100nF

100nF

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