STW81100

16/23

Table 10.

8.1.8 Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data bytes and each

one is acknowledged. The master terminates the transfer by generating a STOP condition.

The sub-address decides the starting byte. A multi byte with sub-address 07H and 5 DATA_IN byte would

affect the bytes starting from DATA_OUT[63:56] to DATA_OUT[31:24] and so on.

Table 11.

8.1.9 Current Byte Address Read

In the current byte address read mode, following a START condition, the master sends the device address

with the rw bit set to 1 (No sub-address is needed as there is only 1 byte read register). The STW81100

acknowledges this and outputs the data byte. The master does not acknowledge the received byte, but

terminates the transfer with a STOP condition.

Table 12.

8.2 Timing Specification

Figure 20. Data and clock

Table 13.

S

0

ack

sub-address byte

ack

DATA IN

ack

P

S

0

ack

sub-address byte

ack

DATA IN

ack

....

DATA IN

ack

P

S

0

ack

sub-address byte

ack

DATA IN

ack

....

DATA IN

ack

P

Symbol

Parameter

Minimum time (ns)

Data to clock set up time

2

Data to clock hold time

2

Clock pulse width high

10

Clock pulse width low

5

t

cs

t

ch

t

cwh

t

cwl

SDA

SCL

t

cs

t

ch

t

cwh

t

cwl

SDA

SCL