M69AR048B

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Table 11. Read Mode AC Characteristics

Note: 1. Maximum value is applicable if E1 is kept Low without change of address input of A3 to A20. If needed by system operation, please

contact your local ST representative for relaxation of the 1000ns limitation.

2. Address should not be changed within minimum Read Cycle Time.

3. The output load 5pF without any other load.

4. Applicable to A3 to A20 when E1 is kept Low.

5. Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access.

6. In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page

Read Cycle must be closed within 4µs.

7. Applicable when at least two of address inputs among applicable are switched from previous state.

8. Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied.

9. Values obtained with AC Measurement Load Circuit 1 (see Figure 5). If the test conditions correspond to AC Measurement Load

Circuit 2 (see Figure 6), 10ns must be added to the times given in the above table.

Symbol

Alt.

Parameter

M69AR048B

Unit

80

85

Min

Max

Min

Max

(1,2,9)

Address Valid Time

80

1000

85

1000

ns

(1,5,6,9)

Page Read Cycle Time

25

1000

30

1000

ns

(1,5,6,9)

Page Read Cycle Time

25

1000

30

1000

ns

Address Valid to Chip Enable Low

–5

–5

ns

(4,9)

Address Valid to Output Valid

1.65V

80

85

ns

1.75V

70

70

ns

(5,9)

Page Address Access Time

20

25

ns

(4,7)

Address Invalid Time

10

10

ns

(5,7)

Page Address Invalid Time

10

10

ns

Data hold from address change

5

5

ns

Upper/Lower Byte Enable High to Output Transition

5

5

ns

Upper/Lower Byte Enable High to Output Hi-Z

20

20

ns

(9)

Upper/Lower Byte Enable Low to Output Valid

30

35

ns

(3)

Upper/Lower Byte Enable Low to Output Transition

0

0

ns

(8)

Chip Enable High to Address Invalid

–5

–5

ns

Chip Enable High to Chip Enable Low

15

15

ns

Chip Enable High to Output Transition

5

5

ns

Chip Enable High to Output Hi-Z

20

20

ns

(1,2)

Read Cycle Time

80

1000

85

1000

ns

(1,2)

Read Cycle Time

80

1000

85

1000

ns

(9)

Chip Enable Low to Output

Valid

1.65V

80

85

ns

1.75V

70

70

(3)

Chip Enable Low to Output Transition

5

5

ns

Output Data Hold Time

5

5

ns

Output Enable High to Output Hi-Z

20

20

ns

(9)

Output Enable Low to Output Valid

45

50

ns

(3)

Output Enable Low to Output Transition

0

0

ns