LTC6902CMS datasheet(10/16 Pages) LINER

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LTC6902

6902f

THEORY OF OPERATIO

by 90 degrees, OUT3 lags OUT2 by 90 degrees and OUT4

lags OUT3 by 90 degrees. The signals are generated by

flip-flops. The output frequency is the programmable

divider’s output further divided 4 (M = 4).

The multiphase mode is determined by the state of the PH

input (Pin 3). Tie the PH pin to GND or drive it below 0.5V

to select the 2-phase mode. The PH pin may be floated or

driven to midsupply to select the 3-phase mode. The

4-phase mode is selected by tying the PH pin to V+ or

driving it to within 0.4V of V+.

The CMOS output drivers have an ON resistance that is

typically less than 100

Ω. In the ÷1 (high frequency) mode,

the rise and fall times are typically 7ns with a 5V supply and

11ns with a 3V supply. These transition times maintain a

clean square wave at 10MHz (20MHz at 5V supply). In the

÷10 and÷100 modes, where the output frequency is much

lower, slew rate control circuitry in the output driver in-

creases the rise/fall times to typically 14ns for a 5V supply

and 19ns for a 3V supply. The reduced slew rate lowers EMI

(electromagnetic interference) and supply bounce.

Spread Spectrum Frequency Modulation

The LTC6902 provides the additional feature of spread

spectrum frequency modulation (SSFM). The oscillator’s

frequency is modulated by a pseudorandom noise (PRN)

signal to spread the oscillator’s energy over a wide fre-

quency band. This spreading decreases the peak electro-

magnetic radiation levels and improves electromagnetic

compatibility (EMC) performance.

The amount of frequency spreading is determined by the

external resistor RMOD and the voltage between the V+ and

MOD pins (V+ – VMOD). Unlike the stationary SET pin

voltage (VSET), the MOD pin voltage (VMOD) is a dynamic

signal generated by a multiplying digital to analog con-

verter (MDAC) referenced to VSET. Referencing to VSET

negates errors due to variations of the VSET voltage and

locks the two voltages together. The VMOD voltage is the

VSET voltage scaled by one fifth and multiplied by the

digital code sent to the MDAC from the pseudorandom

binary sequence (PRBS) generator. VMOD varies in a

pseudorandom noise-like manner. The (V+ – VMOD) volt-

age is 0V minimum and maximally one fifth (20%) of

(V+ – VSET).

Referencing VMOD to VSET allows the ratio of RSET to

RMOD to determine the amount of frequency spreading.

Consider the case when RSET is equal to RMOD. Here,

when the (V+ – VMOD) voltage is at its minimum of 0V,

IMOD = 0A, IMASTER = ISET and the master oscillator is at

its maximum frequency (fMAX) which is the fOUT fre-

quency set by the RSET resistor. Furthermore, when the

(V+ – VMOD) voltage is at its maximum of 20% of (V+ –

VSET), IMOD = 0.2 • ISET, IMASTER = 0.8 • ISET and the

master oscillator is at its minimum frequency (fMIN)

which is 80% of the fOSC frequency set by the RSET

resistor. The general formula for the amount of frequency

spreading is below:

Frequency Spreading (in %) = 20 •

RSET

RMOD

where frequency spreading is defined as:

Frequency Spreading (in %) = 100 •

MAX

–fMIN

The design procedure is to first choose the RSET resistor

value to set fMAX (fOUT) and then choose the RMOD resistor

value to set the amount of frequency spreading desired.

Note that the frequency is always modulated to a lower

value. This is often referred to as a down spread signal.

To disable the SSFM, connect the MOD pin to ground.

Grounding the MOD pin disables the modulation and shuts

down the modulation circuitry. While leaving the MOD pin

open, RMOD = ∞, gives a frequency spreading of 0%, this

is not a good method of disabling the modulation. The

open pin is susceptible to external noise coupling that can

affect the output frequency accuracy. Grounding the MOD

pin is the best way to disable the SSFM.

As stated previously the modulating waveform is a pseu-

dorandom noise-like waveform. The pseudorandom signal

is generated by a linear feedback shift register that is 9 bits

long. The pseudorandom sequence will repeat every 512

(29) shift register clock cycles. The bottom seven bits of the

shift register are sent in parallel to the MDAC which pro-

duces the VMOD voltage. Being a digitally generated signal,

the output is not a perfectly smooth waveform but consists

of 128 (27) discrete steps that change every shift register

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