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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SCF5250EC датащи(PDF) 20 Page - NXP Semiconductors |
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SCF5250EC датащи(HTML) 20 Page - NXP Semiconductors |
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20 / 56 page  SCF5250 Data Sheet: Technical Data, Rev. 1.3 20 Freescale Semiconductor . 3.19 BDM/JTAG Signals The SCF5250 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed with background debug pins. 3.20 Clock and Reset Signals The clock and reset signals configure the SCF5250 processor and provide interface signals to the external system. 3.20.1 Reset In Asserting RSTI causes the SCF5250SCF5250 to enter reset exception processing. When RSTI is recognized, the data bus is tri-stated. Table 12. Processor Status Signal Encodings PST[3:0] Definition (HEX) (BINARY) $0 0000 Continue execution $1 0001 Begin execution of an instruction $2 0010 Reserved $3 0011 Entry into user-mode $4 0100 Begin execution of PULSE and WDDATA instructions $5 0101 Begin execution of taken branch or Synch_PC1 1 Rev. B enhancement. $6 0110 Reserved $7 0111 Begin execution of RTE instruction $8 1000 Begin 1-byte data transfer on DDATA $9 1001 Begin 2-byte data transfer on DDATA $A 1010 Begin 3-byte data transfer on DDATA $B 1011 Begin 4-byte data transfer on DDATA $C 1100 Exception processing2 2 These encodings are asserted for multiple cycles. $D 1101 Emulator mode entry exception processing2 $E 1110 Processor is stopped, waiting for interrupt2 $F 1111 Processor is halted2 |
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