3

Integrated

Circuit

Systems, Inc.

ICS9DB106

Preliminary Product Preview

0833A—07/26/04

The ICS9DB106 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB106 is driven by a differential

SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It

attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without

Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock

request (OE#) pins make the ICS9DB106 suitable for Express Card applications.

General Description

Block Diagram

Power Groups

VDD

GND

7, 13, 16, 22

8,21

PCI Express Outputs

TBD

TBD

SMBUS

N/A

27

IREF

28

27

Analog VDD & GND for PLL core

Description

Pin Number

SPREAD

COMPATIBLE

PLL

CONTROL

LOGIC

SMBDAT

SMBCLK

CLK_INT

C LK_INC

PLL_BW

IREF

PCIEX1

PCIEX4

CLKREQ4#

CLKREQ1#

PCIEX(0,2,3,5)