© 2001 Fairchild Semiconductor Corporation

www.fairchildsemi.com

KA393 / KA2903 • Rev. 1.0.3

5

Physical Dimensions

Figure 10.8-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, .150" Narrow Body

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without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

8°

0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

LAND PATTERN RECOMMENDATION

SEATING PLANE

C

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR

4

8

1

B

5

A

5.60

0.65

1.75

1.27

6.20

5.80

3.81

4.00

3.80

5.00

4.80

(0.33)

1.27

0.51

0.33

0.25

0.10

1.75 MAX

0.25

0.19

0.36

0.50

0.25

R0.10

R0.10

0.90

0.40

(1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

0.25

CB A

0.10 C