TVP3020 datasheet(13/98 Pages) TI

13 / 98 page

1–7

1.5

Terminal Functions (Continued)

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

SFLAG

(TTL

compatible)

Split shift register transfer flag. The Viewpoint VIP detects a

low-to-high transition on this terminal during a blank sequence and

immediately generates an SCLK pulse. This early SCLK pulse

replaces the first SCLK pulse in the normal sequence.

SYSBL

(TTL

compatible)

System blank input. SYSBL is active (low).

SYSHS,

SYSVS

89, 90

(TTL

compatible)

System horizontal and vertical sync inputs. These signals are used to

generate the sync level on the green current output. They are active

(low) inputs, but the HSYNCOUT and VSYNCOUT outputs can be

programmed through general control register.

VCLK

111

(TTL

compatible)

Video clock output. VCLK is the user-programmable output for

synchronization to graphics processor.

VGABL

(TTL

capability)

VGA blank input. VGABL is active (low).

VGAHS,

VGAVS

92, 93

(TTL

capability)

VGA horizontal and vertical sync inputs. These signals are used to

generate the sync level on the green current output. They can be either

polarity, and the VIP passes the polarities to HSYNCOUT and

VSYNCOUT without change.

VGA0 – VGA7

78 – 85

(TTL

capability)

VGA pass-through bus. These buses can be selected as the pixel bus

for VGA mode, but it does not allow for any multiplexing.

VSYNCOUT

(TTL

capability)

Vertical sync output after pipeline delay. For system mode, the output

can be programmed but for the VGA mode, the output carries the

same polarity as the input.

(TTL

capability)

Write strobe input. A logic 0 on this terminal initiates a write to the

initiated on the low-going edge of WR, (see Figure 3–1).

8/6

(TTL

capability)

DAC resolution selection. This terminal is used to select the data bus

width (8 or 6 bits) for the DAC and is essentially provided in order to

maintain compatibility with the IMSG176. When this terminal is a

logical 1, 8-bit bus transfers are used with D7 the MSB and D0 the

LSB. For 6-bit bus operation, while the color palette still has the 8-bit

information D5 shifts to the bit 7 position with D0 shifted to the bit 2

position and the two LSBs are filled with zeros at the output multiplexer

to DAC. The palette holding register zeroes the two MSBs when it is

read in the 6-bit mode.

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

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