TPS3430WDRCR datasheet(22/26 Pages) TI1

22 / 26 page

VDD1

GND

TPS3430

VDD2

1.8 V

Microcontroller

SET1

VCORE

CRST

GND

WDO

NMI

CWD

SET0

WDI

GPIO

0.1 µF

WDO

VDD

WATCHDOG

CONTROL

TPS3430

SBVS366 – JULY 2018

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Product Folder Links: TPS3430

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8.2.1.2.3

Calculating the WDO Pull-up Resistor - Design 1

Figure 19 shows the TPS3430 uses an open-drain configuration for the WDO circuit. When the FET is off, the

resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain

to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that

VOL is below its maximum value. To choose the proper pull-up resistor, there are three key specifications to keep

in mind: the pull-up voltage (VPU), the recommended maximum WDO pin current (IWDO), and VOL. The maximum

VOL is 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin

below 0.4 V with IWDO kept below 10 mA. For this example, with a VPU of 3.3 V, a resistor must be chosen to

keep IWDO below 200 μA because this value is the maximum consumption current allowed. To ensure this

specification is met, a pull-up resistor value of 16.5 kΩ is selected, which sinks a maximum of 200 μA when

WDO is asserted. WDO current is at 200 μA and the low-level output voltage is approximately zero.

Figure 19. Open-Drain WDO Configuration

8.2.2 Monitoring Microcontroller with a Programmed Window Watchdog Timer - Design 2

A typical application for the TPS3430 is shown in Figure 20. The TPS3430 is used to monitor the activity of the

microcontroller via the WDI pin.

Figure 20. Monitoring Microcontroller Using a Window Watchdog Timer with Programmable Watchdog

Reset Delay

8.2.2.1 Design Requirements - Design 2

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Watchdog Reset delay

Minimum reset delay of 250 ms

Minimum reset delay of 260 ms, reset delay of 322

ms (typical)

Watchdog window

Functions with a 30-Hz pulse-width modulation

(PWM) signal with a 50% duty cycle

Leaving the CWD pin unconnected with SET0 = 0

and SET1 = 0 produces a window with a tWDL(max)

of 25.9 ms and a tWDU(min) of 46.8 ms

Output logic voltage

1.8-V CMOS

Maximum device current

consumption

200 µA

10 µA of current consumption, typical worst-case of

199 µA when WDO is asserted

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