AD5263 datasheet(3/6 Pages) AD

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PRELIMINARY TECHNICAL DATA

Quad +15V Digital Potentiometers

AD5263

08 AUG ’02, REV PrD

- 3 -

ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (V

DD = +5V, VSS = -5V, VL = +5V,

VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

SPI (DIS=’0’) INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,12)

Input Clock Pulse Width

tCH,tCL

Clock level high or low

Data Setup Time

tDS

Data Hold Time

tDH

CLK to SDO Propagation Delay13

tPD

RL = 1KΩ, CL < 20pF

150

CS Setup Time

tCSS

CS High Pulse Width

tCSW

Reset Pulse Width

tRS

CLK Fall to

CS Rise Hold Time

tCSH

CS Rise to Clock Rise Setup

tCS1

I2C (DIS=’1’) INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)

SCL Clock Frequency

fSCL

400

KHz

tBUF Bus free time between STOP & START

1.3

µs

tHD;STA Hold Time (repeated START)

After this period the first clock pulse is generated

0.6

µs

tLOW Low Period of SCL Clock

1.3

µs

tHIGH High Period of SCL Clock

0.6

µs

tSU;STA Setup Time For START Condition t5

0.6

µs

tHD;DAT Data Hold Time

0.9

µs

tSU;DAT Data Setup Time

100

tF Fall Time of both SDA & SCL signals

300

tR Rise Time of both SDA & SCL signals

300

tSU;STO Setup time for STOP Condition

t10

0.6

µs

NOTES:

Typicals represent average readings at +25°C and VDD = +5V, VSS = -5V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the

relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+5V, VSS=-5V.

VAB = VDD, Wiper (VW) = No connect

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.

DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.

Worst case supply current consumed when input all logic-input levels set at 2.4V, standard characteristic of CMOS logic.

PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.

10.

All dynamic characteristics use VDD = +5V, VSS = -5V, VL = +5V.

11.

Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.

12.

See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics

are measured using VL = +5V.

13.

Propagation delay depends on value of VDD, RL, and CL see applications text.

14.

The AD5260/AD5262 contains 1,968 transistors. Die Size: 89mil x 105mil, 9,345sq. mil.

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