PC87322VF datasheet(52/84 Pages) NSC

52 / 84 page

60 Serial Ports (Continued)

TABLE 6-3 PC87322VF UART Reset Configuration

l Signal

Reset Control

Reset State

Interrupt Enable Register

Master Reset

0000

0000 (Note 1)

Interrupt Identification Register

Master Reset

0000 0001

FIFO Control

Master Reset

0000 0000

Line Control Register

Master Reset

0000 0000

MODEM Control Register

Master Reset

000

0 0000

Line Status Register

Master Reset

110 0000

MODEM Status Register

Master Reset

XXXX

0000 (Note 2)

SOUT

Master Reset

High

INTR (RCVR Errs)

Read LSR

l MR

LowTRI-STATE

INTR (RCVR Data Ready)

Read RBR

l MR

LowTRI-STATE

INTR (THRE)

Read IIR

l Write THR l MR

LowTRI-STATE

INTR (Modem Status Changes)

Read MSR

l MR

LowTRI-STATE

Interrupt Enable Bit

Master Reset

Low

RTS

Master Reset

High

DTR

Master Reset

High

RCVR FIFO

MRFCR1

FCR0FCR0

All Bits Low

XMIT FIFO

MRFCR1

FCR0FCR0

All Bits Low

Note 1

Boldface bits are permanently low

Note 2

Bits 7–4 are driven by the input signals

Bit 4

This bit is the Even Parity Select bit When parity is

enabled and bit 4 is a logic 0 an odd number of

logic 1s is transmitted or checked in the data word

bits and Parity bit When parity is enabled and bit 4

is a logic 1 an even number of logic 1s is transmit-

ted or checked

Bit 5

This bit is the Stick Parity bit When parity is en-

abled it is used in conjunction with bit 4 to select

Mark or Space Parity When LCR bits 3 4 and 5

are logic 1 the Parity bit is transmitted and

checked as a logic 0 (Space Parity) If bits 3 and 5

are 1 and bit 4 is a logic 0 then the Parity bit is

transmitted and checked as a logic 1 (Mark Pari-

ty) If bit 5 is a logic 0 Stick Parity is disabled

Bit 6

This bit is the Break Control bit It causes a break

condition to be transmitted to the receiving UART

When it is set to a logic 1 the serial output (SOUT)

is forced to the Spacing state (logic 0) The break

is disabled by setting bit 6 to a logic 0 The Break

Control bit acts only on SOUT and has no effect

on the transmitter logic

Note

This feature enables the CPU to alert a terminal If the

following sequence is used no erroneous characters will

be transmitted because of the break

1 Wait for the transmitter to be idle (TEMT e 1)

2 Set break for the appropriate amount of time If

the transmitter will be used to time the break

duration then check that TEMT e 1 before

clearing the Break Control bit

3 Clear break when normal transmission has to

be restored

During the break the Transmitter can be used as

a character timer to accurately establish the break

duration by sending characters and monitoring

THRE and TEMT

Bit 7

This bit is the Divisor Latch Access Bit (DLAB) It

must be set high (logic 1) to access the Divisor

Latches of the Baud rate Generator during a Read

or Write operation or to have the BOUT signal ap-

pear on the BOUT pin It must be set low (logic 0)

to access any other register

623 Programmable Baud Rate Generator

The PC87322VF contains two independently programmable

Baud rate Generators The 24 MHz crystal oscillator fre-

quency input is divided by 13 resulting in a frequency of

18462 MHz This is sent to each Baud rate Generator and

divided by the divisor of the associated UART The output

frequency of the Baud rate Generator (BOUT12) is 16 c

the baud rate

divisor

(frequency input) (baud rate c 16)

The output of each Baud rate Generator drives the transmit-

ter and receiver sections of the associated serial channel

Two 8-bit latches per channel store the divisor in a 16-bit

binary format These Divisor Latches must be loaded during

initialization to ensure proper operation of the Baud rate

Generator Upon loading either of the Divisor Latches a

16-bit Baud Counter is loaded Table 6-4 provides decimal

divisors to use with crystal frequencies of 24 MHz The os-

cillator input to the chip should always be 24 MHz to ensure

that the Floppy Disk Controller timing is accurate and that

the UART divisors are compatible with existing software

Using a divisor of zero is not recommended

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