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PC8260 датащи(PDF) 3 Page - ATMEL Corporation |
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PC8260 датащи(HTML) 3 Page - ATMEL Corporation |
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3 / 53 page ![]() 3 PC8260 PowerQUICC II 2131B–HIREL–02/03 PC8260 Architecture General Overview The PC8260 has two external buses to accommodate bandwidth requirements from the highspeed system core and the very fast communications channels. The device is com- posed of the following three major functional blocks: • A 64-bit PowerPC core derived from the EC603e with MMUs and caches. • A system interface unit (SIU). • A communications processor module (CPM). Both the system core and the CPM have an internal PLL, which allows independent optimization of the frequencies at which they run. The system core and CPM are both connected to the 60x bus. Figure 1. PC8260 Block Diagram MCC MCC FCC FCC FCC SCC SCC SCC SCC SMC SMC SPI Clock Counter Memory Controller Bus Interface Unit System Functions 60x-to-Local Bus Bridge 60x-to-PCI Bus Bridge (PC8265 only) I C 2 PCI/ Local Bus Time Slot Assigner Serial Interface 8 TDMs 2 UTOPIA 3 Mlls Non-Multiplexed I/O 60x Bus 16-Kbyte Instruction Cache 16-Kbyte Data Cache IMMU DMMU EC603e PowerPC Core Timers Parallel I/O Baud Rate Generator Interrupt Controller 24-Kbyte Dual- Port RAM 32-Bit RISC Communications Processor (CP) and Program ROM Serial DMAs 4 Virtual IDMAs |
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