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Preliminary Data Sheet

3

International

Rectifier

IRVR101

Interface Design

The interface design is based on the LIN communication protocol.

Detailed information regarding this

communication protocol can be found in the latest revision of the LIN Specification Package. This package can

be obtained from the LIN Website located at www.lin-subbus.org.

Activation and De-activation

The voltage regulator is activated by a wake up signal that consists of the character ‘0x80’. The regulator is

also capable of

waking up with the presence of any normal bus activity.

Once the regulator has been

activated, the regulator will wait until a valid message is received prior to turning on the field driver. The

regulator will then hold the field duty cycle at 18.75% until a cut-in phase signal is recognized at which time the

regulator will soft start ramp to normal regulation. The cut-in phase voltage and frequency must be greater than

2V and 1200 Generator RPM (GRPM) respectively. De-activation requires a bus timeout in combination with a

phase signal timeout. Bus timeout occurs 2s after the last valid message is received. Phase signal timeout

occurs 500mS after the phase voltage and frequency have fallen below 0.6V AND 600 GRPM, respectively.

Self-excitation

In the event of a LIN bus fault, the voltage regulator is capable of self-excitation if a phase voltage and

frequency of greater than 0.6VAND 1200 Generator RPM is detected.

This signal is only possible if the

residual magnetism in the alternator rotor core is sufficient enough to generate a magnetic field capable of

inducing the voltage signal in the stator windings. If this signal is detected, the regulator will apply an 18.75%

duty cycle until the cut-in phase signal is recognized at which time the regulator will soft start ramp to default

regulation.

The regulator will return to sleep mode at any time when the phase signal has timed out as

described above.

Voltage Sensing

System voltage sensing can be achieved via the dedicated battery sense input or through machine sensing

from the rectifier B+ output via the F+ input to the regulator. The battery sense input is optional and can be

deleted. If the battery sense option is exercised, an open or short circuit at this input will cause voltage sensing

to transfer to the machine voltage sense input (an electrical fault can be indicated if the regulator is configured

for this fault option). The machine voltage setpoint can be set to a different value than the battery sense voltage

to compensate for system voltage variation between the alternator and the battery.

Voltage Regulation

Voltage regulation is achieved using fixed frequency pulse width modulation. The base frequency is typically

150 Hz and the proportional control range for regulation is 100mV. This provides for very stable regulation over

the entire speed and electrical load range.

Load Response Control

Load response control is programmable and can be varied from 0.426 seconds to 13.2 seconds in 16 steps.

Additionally, the load response control cut-off speed is programmable and can be set to “always active” or

varied from 2400 to 8000 Generator RPM. The load response at startup is equal to the programmed value for

the load response control. The load response will always be executed on the first ramp to full field after engine

start regardless of frequency in order to assist in achieving a smooth engine start.

Fault Detection

Respective fault codes are transmitted per the “Fault Detection” table. A 500mS delay is enforced prior to the

transmission of any fault code. Mechanical faults are based on the frequency detection of the stator phase

signal. Electrical faults are based on the voltage detection of the stator phase and system voltage sense inputs.

A temperature fault is based on the regulator IC junction temperature. Communication errors are detected after

a delay of 2s. Examples of sync communication errors are sync bit, checksum, and bit detect errors. A sync bit

error is detected when the sync field does not = ‘0x55’. A checksum error is generated when the sum of the

modulo-256 sum over all data bytes and the checksum byte do not equal ‘0xFF’. A bit error is detected when a

transmitted bit does not correspond to the appropriate bus state due to another device forcing the bus to a