IR3086

Page 11 of 15

9/1/03

IR3086 THEORY OF OPERATION

Block Diagram

The Block diagram of the IR3086 is shown in figure 6 and specific features discussed in the following section.

+

-

10K

+

-

+

-

+

-

+

-

+

-

VCC

RMPIN+

RMPIN-

EAIN

ISHARE

PWMRMP

SCOMP

BIASIN

LGND

GATEH

VCCH

PGND

GATEL

CSIN+

VCCL

HOTSET

VRHOT

PHSFLT

DACIN

CSIN-

INTERNAL

CIRCUIT

BIAS

RAMP

COMPARATOR

CLOCK

PULSE

GENERATOR

SHARE

ADJUST

ERROR

AMP

RAMP

SLOPE

ADJUST

20mV

PWM

LATCH

RESET

PWM

COMPARATOR

DOMINANT

S

R

0% DUTY

CYCLE

COMPARATOR

SYSTEM

REFERENCE

VOLTAGE

X

0.91

GATE

NON-OVERLAP

COMPARATORS

CURRENT

SENSE

AMP

X34

2V

OVP

COMPARATOR

VOLTAGE

PROPORTIONAL

TO ABSOLUTE

TEMPERATURE

ENABLE

RAMP

DISCHARGE

CLAMP

FAULT

COMPARATOR

130mV

+

+

VRHOT

COMPARATOR

Figure 6 – IR3086 Block Diagram

Tri-State Gate Drivers

The gate drivers can deliver up to 3A peak current. An adaptive non-overlap circuit monitors the voltage on the

GATEH and GATEL pins to prevent MOSFET shoot-through current while minimizing body diode conduction.

An Enable signal is provided by the Control IC to the Phase IC without the additional of a dedicated signal line. The

Error Amplifier output of the Control IC drives low in response to any fault condition such as input under voltage or

output overload. The IR3086 0% duty cycle comparator detects this and drives both gate outputs low. This tri-state

operation prevents negative inductor current and negative output voltage during power-down.

The Gate Drivers revert to a high impedance “off” state at VCCL and VCCH supply voltages below the normal

operating range. An 80kΩ resistor is connected across the GATEX and PGND pins to prevent the GATEX voltage

from rising due to leakage or other cause under these conditions.