ESS Technology, Inc.

SAM0341-041101

3

ES2839/ES2840 PRODUCT BRIEF

PIN DESCRIPTIONS

Table 1 lists the ES2839 pin descriptions, and Table 2 lists the

ES2840 pin descriptions.

Table 1 ES2839 Pin Descriptions

Name

Pin Number

I/O

Definitions

C/BE3:0#

1, 13, 21, 31

I/O

Multiplexed bus command/byte enable pins. These pins indicate cycle type during the address phase of a transaction.

They indicate active-low byte enable information for the current data phase during the data phases of a transaction.

These pins are inputs during slave operation and outputs during bus mastering operation.

IDSEL

2

I

Initialization device select, active-high. This pin is used as a chip select during PCI configuration read and write cycles.

GND

3, 15, 22, 41,

52, 61, 64, 91

G

Digital ground.

AD31:0

4:11, 23:30,

33:40, 92:99,

I/O

Address and data pins AD31:0.

VDD

12, 32, 46, 51,

58, 89, 100

P

Digital voltage pins [VDD (3.3V)].

FRAME#

14

I/O

Cycle frame, active-low. The current PCI bus master drives this pin to indicate the beginning and duration of a

transaction.

IRDY#

16

I/O

Initiator ready, active-low. The current PCI bus master drives this pin to indicate that, as the initiator, it is ready to transmit

or receive data (and complete the current data phase).

TRDY#

17

I/O

Target ready, active-low. The current PCI bus master drives this pin to indicate that, as the target device, it is ready to

transmit or receive data (and complete the current data phase)

DEVSEL#

18

I/O

Device select, active-low. The PCI bus target device drives this pin to indicate that it has decoded the address of the

current transaction as its own chip select range.

STOP#

19

I/O

Stop transaction, active-low. The current PCI bus target drives this pin active to indicate a request to the master to stop

the current transaction.

PAR

20

I/O

Parity, active-high. Indicates even parity across AD[31:0] and C/BE[3:0]# for both address and data phases. The signal is

delayed one PCI clock from either the address or data phase for which parity is generated.

SEDO

42

I

Serial EPROM data output pin with internal pullup.

SEDI

43

O

Serial EPROM data input.

SECLK

44

O

Serial EPROM data clock input pin with internal pulldown.

SECS

45

O

Serial EPROM chip select pin with internal pulldown.

PF[9:7],

PF[5:4] and

PF[2]

47, 49, 50,

55:53,

I/O

PF2, PF4, PF5, and PF[7:9] general-purpose programmable bidirectional flag pins. Can be used for interfacing with a

telephone or other device, performing such functions as phone-off-hook, phone-on-hook, ring, and caller ID. Refer to pin

descriptions of pins 48 and 57 for preprogrammed telephone interface pins.

LCS/PF3

48

I

Local current sense input, pulled to ground through 4.7k

Ω resistor. Otherwise, is PF# general-purpose programmable

flag I/O pin.

DSPK/PF11

57

I/O

DSPK/PF11 modem speaker digital output.

OSCI

59

I

18.816-MHz crystal oscillator input.

OSCO

60

O

18.816-MHz crystal oscillator output.

D[6:5]

63, 64

I/O

Isolation signal outputs.

AVDD

65, 82

P

Analog voltage pins [AVDD (5V)].

AGND

68, 81

G

Analog ground.

NC

66, 67, 75, 76

I

No connect.

KRXP

69

O

Low-voltage DAA analog differential positive output.

KRXN

70

O

Low-voltage DAA analog differential negative output.

RXN

71

I

Codec analog differential negative input. The DC level is Vcm, and the full-scale input is either 0.22 Vp-p ±5% or 1.1V

p-p±5%, depending on the gain setting.

RXP

72

I

Codec analog differential positive input. The DC level is Vcm, and the full-scale input is either 0.22 Vp-p ±5% or 1.1V

p-p±5%, depending on the gain setting.

VREF

73

O

Voltage reference bypass. Has a range of 1.2356V±5%. Bypass to AGND with 0.1-

µF ceramic chip capacitor parallel

with 10-

µF tantalum capacitor.

VCM

74

O

Common mode voltage bypass. Has a range of 2.16V±5%. Bypass to AGND with 0.1-

µF ceramic chip capacitor parallel

with 10-

µF tantalum capacitor.

KTXP

77

I

Low-voltage DAA analog differential positive input.