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CS7622 датащи(PDF) 10 Page - Cirrus Logic |
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CS7622 датащи(HTML) 10 Page - Cirrus Logic |
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10 / 36 page ![]() CS7622 10 DS322PP1 matically biased to mid-supply without worrying about external circuitry to perform this task. 3.2 Black Level Adjustment In order to maintain a constant reference level for black pixels, a feedback loop is implemented that sets the black level value at the output of the ADC to 64 in the 13 bit digital code. This loop is active during the optically black pixels which are output at the beginning and end of a frame as well as dur- ing a portion of the horizontal blanking period. The presence of black pixels in the CCD output is indi- cated by the CLAMP pulse, which is supplied ex- ternally through the CLAMP pin. The black level can also be written to through the serial port. In order to acquire a starting value for the black lev- el, the loop will run over the several lines of black pixels at the beginning of the frame. The block di- agram of the loop is shown in Figure 10. The up- date rate is once per line during active pixel lines as long as the Clamp pulse is < n+10 cycles. Where n is the number of pixels accumulated before the black loop is updated and is programmable through register 0Dh bits 5:0. If the Clamp pulse is longer than n+10 cycles the black loop is updated every n+10 cycles. For example, during optical back lines the loop is updated several times at a rate of once every n+10 cycles. The open-loop transfer function of the black level adjustment loop is blk_gain = 1, 2, 4, or 8 where blk_gain is programmable through a register and n = # of black pixels during clamp time, which is also programmable. The value of Kxn will deter- mine the open-loop gain of the system. The settling time for the loop can be calculated using the fol- lowing formula: For offset range=1 (reg 06h, bit 0) For offset range =0 CCD INPUT SIGNAL ck_ft ck_data OUT OF STAGE 1 OUT OF STAGE 2 OUT OF STAGE 3 Figure 9. Idealized timing diagram of VGA/CDS circuit V(1) V(2) V(3) V(1) V(2) V(3) V(1) V(2) V(3) V(1) V(2) Hz () Kn × z1 – ------------- = K 1 256 --------- blk_gain = τ 1 1nK – () ln --------------------------- – 1 fu ----- = τ 1 1 nK 2 ------- – ln ---------------------------- – 1 fu ----- = |
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